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Semiconductor Manufacturing, IEEE Transactions on

Issue 3 • Date Aug 2002

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Displaying Results 1 - 7 of 7
  • Optimal scheduling techniques for cluster tools with process-module and transport-module residency constraints

    Page(s): 341 - 349
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    This paper discusses two scheduling techniques for dual-arm cluster tools that address both process-module and transport-module residency constraints and throughput requirements. The first technique is the extension of our previous work that only addressed process-module residency constraints. For cases with long process times, this technique can take a long time to find the solution and is not practical. Hence, we use this algorithm mainly as a benchmark for comparison. The second technique that uses a linear programming technique with use of several heuristics can find the optimal solution very efficiently. Analytical and experimental analysis of this technique shows the correctness, completeness and efficiency of this technique. View full abstract»

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  • Obtaining silicide free spacers by optimizing sputter etch for deep submicron CMOS processes

    Page(s): 350 - 354
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (221 KB) |  | HTML iconHTML  

    In this paper, we have shown that the sputter etch before cobalt deposition during the silicide processing of a deep submicron CMOS device fabrication needs to be optimized in order to eliminate a detrimental origin of gate (G) to source (S)/drain (D) bridging. It is known that Co cannot reduce even a thin layer of native oxide. Therefore, it is necessary to ensure that Co is deposited on a very clean Si surface. To ensure this, an in-situ sputter etch is commonly conducted before Co deposition. It is observed that this sputter etch process can sputter Si from the S/D area and deposit them on the sidewall spacer (SWS). This sputtered Si in turn will react with deposited Co and form silicide. The worst case leakage currents from poly-Si to composite for long (10 m) and narrow (0.18 micron) poly lines are shown to be on the order of milliampere. Transmission electron microscope (TEM) micrographs included show the existence of cobalt silicide layers (∼8 nm thick) over sidewall spacer. The silicide thickness on the sidewall spacer is correlated with resistance value calculated from current and voltage (I-V) measurements. The need for optimizing the sputter etch recipe has been validated by TEM and I-V measurements. View full abstract»

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  • Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability

    Page(s): 355 - 365
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (694 KB)  

    Two technologies are introduced that, together, provide a platform for robust evaluation of interconnect reliability. One is the DISMAP technology, which provides plots of the displacement and strain fields of cross-sectioned interconnect structures under various loading conditions. Measurements provided by DISMAP reveal how multilevel-interconnect structures interact structurally, for example what type of strain fields exist during thermal cycling. A complimentary technology, known as probabilistic analysis, is also described and applied using the NESSUS software. Probabilistic analysis combines statistical uncertainty with physics-based models to predict the probability of failure and also to reveal the relative importance of the various uncertainties associated with interconnect manufacturing. By comparing the predictions of physical models to DISMAP measurements, the validity of those models are evaluated. View full abstract»

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  • Resist film uniformity in the microlithography process

    Page(s): 323 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    With the trends toward smaller feature size, one of the challenge is to control the resist thickness and uniformity to a tight tolerance in order to minimize thin film interference effects on the critical dimensions. In this paper, we propose a new approach to improve resist thickness control and uniformity through the soft-bake process. Using an array of thickness sensors, a multizones bakeplate and a sliding mode control algorithm, the temperature distribution of the bakeplate is manipulated in real-time to reduce the resist thickness nonuniformity. The sliding mode control algorithm is implemented in a cascaded control structure so that the bake temperature is constrained. This is to prevent decomposition of the photoactive compound in the resist. We have experimentally demonstrated an improvement in the resist thickness uniformity across individual wafers and from wafer-to-wafer. The cascaded control structure using a sliding mode control algorithm provides a simpler and faster implementation of the thickness control strategy and makes it more suitable for real-time application. There is about 75 times reduction in the computation time and a resist thickness nonuniformity of less than 10 Å is achieved. View full abstract»

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  • Nonlinear modeling and multivariable control of photolithography

    Page(s): 310 - 322
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (481 KB)  

    This paper describes a novel approach for the control of the entire photolithography track using a combination of two methods: genetic programming (GP) and nonlinear model predictive control (NMPC). Here, the GP-NMPC approach is used to derive a multivariable control system to ensure the adequate regulation of the printed line width or critical dimension (CD) measured by metrology at the tail of the track. The genetic program is an optimization method motivated by natural evolution, which generates a model that best predicts the effect of process inputs on outputs. When applied to a simulated photolithography track, it identifies which of the process inputs have the greatest effect on CD and suggests the best empirical nonlinear model relating the inputs to the CD, which is then used in the development of the NMPC. Simulation runs using the multivariable controller demonstrate its superiority over that of a conventional feedback approach involving single-loop control. Since the multivariable control uses all available degrees-of-freedom and is designed to account for manipulated variable constraints, it enables the track to cope with unmeasured step- and drift-type disturbances of significantly greater magnitude. View full abstract»

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  • Evaluation of capacity planning practices for the semiconductor industry

    Page(s): 331 - 340
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB) |  | HTML iconHTML  

    We perform four experiments to evaluate several features of capacity planning approaches used in practice and make concrete suggestions for practitioners. We use an optimal capacity planning technique (FIFEX) with industrial demand and capacity data for realistic conclusions. The first experiment studies the cost effects of allowing for capacity expansion only at special times such as at the beginning of each month or each quarter. We find that these effects are not great if there is at least one capacity expansion opportunity about every six months. The second experiment determines the cost implications of capacity planning heuristics. We demonstrate that FIFEX delivers solutions which cost 5-10% less than heuristic solutions. The third experiment examines the sensitivity of costs against the frequency of forecasting and planning. Our experiments indicate that costs can be decreased by 2%-7% by doubling forecasting and planning frequency. We suggest that practitioners forecast and plan at least once every quarter. The final experiment compares joint optimization of tool and floor-shell expansions with sequential optimization. 3%-9% of costs can be saved by using the joint optimization technique FIFEX instead of sequential optimization. We note that although cost savings are relatively small in percentages, they correspond to tens of million dollars. View full abstract»

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  • Model-based uniformity control for epitaxial silicon deposition

    Page(s): 295 - 309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (514 KB) |  | HTML iconHTML  

    Semiconductor fabrication requires tight specification limits on thickness and resistivity for epitaxially deposited silicon films. Our testbed system for integrated, model-based, run-to-run control of epi films incorporates a Centura tool with an epi deposition chamber, an in-line epi film thickness measurement tool, and off-line thickness and resistivity measurement systems. Automated single-input-single-output, run-to-run control of epi thickness has been successfully demonstrated. An advanced multi-objective controller is described, which seeks to provide simultaneous epi thickness control on a run-to-run basis using the in-line sensor, as well as combined thickness and resistivity uniformity control on a lot-to-lot basis using off-line thickness and resistivity sensors. Control strategies are introduced for performing combined run-to-run and lot-to-lot control, based on the availability of measurements. Techniques are proposed for dealing with multiple site measurements of multiple film characteristics taken at different sampling rates, as well as the use of time-based inputs and rate-based models. These concepts are widely applicable for semiconductor fabrication processes. View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
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University of Arizona
Tucson, AZ  85721