Issue 3 • Date Aug 2002
Filter Results
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Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability
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PDF (694 KB)
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Obtaining silicide free spacers by optimizing sputter etch for deep submicron CMOS processes
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PDF (221 KB)
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Optimal scheduling techniques for cluster tools with process-module and transport-module residency constraints
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PDF (359 KB)
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Aims & Scope
IEEE Transactions on Semiconductor Manufacturing addresses innovations of interest to the integrated circuit manufacturing researcher and professional.
Meet Our Editors
Editor-in-Chief
Dr. Sean P. Cunningham
Intel Corporation
RN4-80
2200 Mission College Boulevard
Santa Clara, CA 95054 95054 USA
sean.p.cunningham@intel.com
Phone:+1 408-653-5955


