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IEE Proceedings E - Computers and Digital Techniques

Issue 6 • Nov 1990

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Displaying Results 1 - 8 of 8
  • Hidden assumptions in cryptographic protocols

    Publication Year: 1990, Page(s):433 - 436
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (424 KB)

    It is shown that some well known cryptographic protocols for authentication are insecure if the underlying cryptographic algorithm does not avoid certain special features. Explicit assumptions based on the fundamental properties of cryptographic transformations are recommended as a basis for cryptographic protocol design. It is shown how these properties may be used to design alternative forms of ... View full abstract»

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  • Broadcasting algorithm in computer networks: accumulative depth

    Publication Year: 1990, Page(s):427 - 432
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (464 KB)

    Introduces the concept of accumulative depth of a node in a computer network. By utilising this concept as a criterion in the assignment of weights to the nodes of the network, the authors develop an efficient algorithm (NOBF) to calculate a near-optimal broadcasting figure (a broadcast with a near-minimal transmission delay) in arbitrary point-to-point computer networks. Static and dynamic assign... View full abstract»

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  • Improved performance token ring network interface adapter

    Publication Year: 1990, Page(s):421 - 426
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (532 KB)

    Presents and discusses an improved performance token ring network interface adapter. The description includes that of the adapter architecture, the internal serial bus structure, and the dual latency data path bypass circuitry. It is shown that these enhancements lead to improvements in the performance measures of interest for real-time applications. Critical portions of the circuit were fabricate... View full abstract»

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  • Design and implementation of a family of reliable systolic correlators

    Publication Year: 1990, Page(s):409 - 420
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (988 KB)

    A methodology is presented for adding varying amounts of fault and defect tolerance to computing systems based on linear pipelines. This is illustrated by the example of a novel-architecture correlator/convolver. This new device is described fully, followed by a description of the authors' fault-tolerant technique, based on the idea of an 'interconnection harness'. It is then shown how this method... View full abstract»

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  • Scheme for designing concurrent checking and easily testable PLAs

    Publication Year: 1990, Page(s):442 - 450
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (728 KB)

    The existing concurrent checking schemes for PLAs are based on the assumption that a single fault can occur during normal operation. However, in practice, after a PLA has been fabricated it may contain more than one fault. In certain cases such faults mask each other, e.g. a fault in the functional part of the self-checking PLA may be masked by a fault in the checker. Thus, after a self-checking P... View full abstract»

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  • Reprogrammable FPLA with universal test set

    Publication Year: 1990, Page(s):437 - 441
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (436 KB)

    A field programmable logic array is presented which can be programmed. This FPLA uses one-transistor reprogrammable switches instead of fuses. The FPLA design presented here is also easily testable. In this design, the PLA is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Furthermore, parallelism is employed during testing, and thus... View full abstract»

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  • MOSYN: a MOS circuit synthesis program employing 3-way decomposition and reduction based on seven-valued logic

    Publication Year: 1990, Page(s):451 - 461
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (860 KB)

    A novel circuit synthesis method is proposed in which a 3-way decomposition and reduction procedure is used recursively for a given logic function. Logic functions are described and manipulated using a 7-valued logic system to exploit such advantages as bidirectional conductivity of MOS networks. A circuit synthesis program (MOSYN) based on this method was implemented on VAX/UNIX and was able to g... View full abstract»

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  • Graphical representation of a hardware description language

    Publication Year: 1990, Page(s):462 - 467
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (568 KB)

    A set of tools are presented which are aimed at producing graphical representations of a number of aspects of the behaviour and structure of hardware designs expressed in the hardware description language STRICT. Three main types of diagrams are described. First, a structural diagram in which the implementation of a block in terms of sub-blocks and their interconnection is shown; secondly, a contr... View full abstract»

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Aims & Scope

Published from 1980-1993, IEE Proceedings E contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

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