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Computers and Digital Techniques, IEE Proceedings E

Issue 6 • Date Nov 1990

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Displaying Results 1 - 8 of 8
  • Broadcasting algorithm in computer networks: accumulative depth

    Page(s): 427 - 432
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    Introduces the concept of accumulative depth of a node in a computer network. By utilising this concept as a criterion in the assignment of weights to the nodes of the network, the authors develop an efficient algorithm (NOBF) to calculate a near-optimal broadcasting figure (a broadcast with a near-minimal transmission delay) in arbitrary point-to-point computer networks. Static and dynamic assignments of weights have been considered. The authors analyse the efficiency of the algorithm based on accumulative depth as a function of the transmission delay and the algorithmic complexity. View full abstract»

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  • Reprogrammable FPLA with universal test set

    Page(s): 437 - 441
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A field programmable logic array is presented which can be programmed. This FPLA uses one-transistor reprogrammable switches instead of fuses. The FPLA design presented here is also easily testable. In this design, the PLA is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Furthermore, parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA. View full abstract»

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  • Improved performance token ring network interface adapter

    Page(s): 421 - 426
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    Presents and discusses an improved performance token ring network interface adapter. The description includes that of the adapter architecture, the internal serial bus structure, and the dual latency data path bypass circuitry. It is shown that these enhancements lead to improvements in the performance measures of interest for real-time applications. Critical portions of the circuit were fabricated using a laser direct-write gate array metallisation system. The interface adapter performance results, based on both logic simulation results and timing measurements made on the fabricated chips, are also described. Network performance results are presented, based on a network simulation incorporating the characteristics of the improved network interface adapter. The reported results show a significant performance improvement, specifically, a reduction in mean message waiting time, which is particularly important for applications of token ring networks requiring time-critical performance. View full abstract»

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  • Scheme for designing concurrent checking and easily testable PLAs

    Page(s): 442 - 450
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    The existing concurrent checking schemes for PLAs are based on the assumption that a single fault can occur during normal operation. However, in practice, after a PLA has been fabricated it may contain more than one fault. In certain cases such faults mask each other, e.g. a fault in the functional part of the self-checking PLA may be masked by a fault in the checker. Thus, after a self-checking PLA has been fabricated, it must be tested in the off-line mode to detect all single faults in both the functional part and checker(s), before it can be used in the concurrent checking mode. In the paper, the authors present a new technique for designing self-checking PLAs which are easily testable in the off-line test mode and execute concurrent checking during the normal operation. A design example shows that the overall performance of the proposed technique for large PLAs in terms of area overhead (including routing), delay, and fault-detection capability is better than any of the schemes currently available. View full abstract»

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  • MOSYN: a MOS circuit synthesis program employing 3-way decomposition and reduction based on seven-valued logic

    Page(s): 451 - 461
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (860 KB)  

    A novel circuit synthesis method is proposed in which a 3-way decomposition and reduction procedure is used recursively for a given logic function. Logic functions are described and manipulated using a 7-valued logic system to exploit such advantages as bidirectional conductivity of MOS networks. A circuit synthesis program (MOSYN) based on this method was implemented on VAX/UNIX and was able to generate a set of possible circuits under several constraints, which are equivalent in logic but have different topologies. The algorithm is applicable not only to CMOS static circuits but also to other static and dynamic circuits, including NMOS and cascode voltage switch logic. View full abstract»

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  • Graphical representation of a hardware description language

    Page(s): 462 - 467
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    A set of tools are presented which are aimed at producing graphical representations of a number of aspects of the behaviour and structure of hardware designs expressed in the hardware description language STRICT. Three main types of diagrams are described. First, a structural diagram in which the implementation of a block in terms of sub-blocks and their interconnection is shown; secondly, a control flow diagram is presented as a Petri net giving the control behaviour; and finally a resource usage diagram illustrates the results of exercising a particular block in terms of the silicon area occupied and the time required to compute the result. The information presented in graphical form is that described by the source language, but the graphics provide a more easily comprehensible medium. View full abstract»

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  • Design and implementation of a family of reliable systolic correlators

    Page(s): 409 - 420
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (988 KB)  

    A methodology is presented for adding varying amounts of fault and defect tolerance to computing systems based on linear pipelines. This is illustrated by the example of a novel-architecture correlator/convolver. This new device is described fully, followed by a description of the authors' fault-tolerant technique, based on the idea of an 'interconnection harness'. It is then shown how this methodology can be applied to the architecture of the correlator giving a family of highspeed devices with varying amount of fault tolerance and hardware overhead. In conclusion, an actual implementation using the ES2 Solo 1200 system of one of the members of this family is described and performance/area results are given. View full abstract»

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  • Hidden assumptions in cryptographic protocols

    Page(s): 433 - 436
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    It is shown that some well known cryptographic protocols for authentication are insecure if the underlying cryptographic algorithm does not avoid certain special features. Explicit assumptions based on the fundamental properties of cryptographic transformations are recommended as a basis for cryptographic protocol design. It is shown how these properties may be used to design alternative forms of the protocols analysed. View full abstract»

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