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Circuits, Devices and Systems, IEE Proceedings -

Issue 2 • Date Apr 2002

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Displaying Results 1 - 7 of 7
  • Advanced SPICE modelling of SiGe HBTs using VBIC model

    Page(s): 129 - 135
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (695 KB)  

    The vertical bipolar intercompany (VBIC) model has been applied to silicon-germanium heterojunction bipolar transistors (SiGe HBTs). The model includes the improved Early effect, quasi-saturation, substrate parasitic, avalanche multiplication, and self-heating. Several device parameters have been extracted from SiGe HBTs and implemented in the VBIC model. A comparison is made with the SPICE Gummel-Poon model. The usefulness and accuracy of the VBIC model for SiGe HBTs are demonstrated by way of comparison of simulated and measured room temperature device data View full abstract»

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  • Experimental 128-kbit ferroelectric memory with 1012 endurance and 10-year data retention

    Page(s): 136 - 142
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (878 KB)  

    An experimental 128-kbit ferroelectric random access memory is presented, which has been designed and fabricated with 0.5 μm ferroelectric storage cell integrated CMOS technology. To achieve stable cell operation, novel design techniques, robust to unstable cell capacitors, are adopted: open bit-line cell array; up-down pulsed plate read/write-back scheme; complementary data preset reference circuitry; and non-ferroelectric reference voltage generator. A self-driven cell plate scheme has also been employed to improve cell array layout efficiency. The prototype chip incorporating these circuit schemes shows 70 ns access time and 120 ns cycle time at 3.3 V and 25°C. The read/write endurance has been confirmed up to 1012 cycles. It has also been observed that memory cells can retain the data for 10 years View full abstract»

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  • Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis

    Page(s): 97 - 104
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (900 KB)  

    The paper presents a novel graph-based evolutionary optimisation technique called evolutionary graph generation (EGG) and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. A unique feature of EGG is its capability to handle the general graph structures directly in the evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. The paper also demonstrates that the evolution process of EGG can be accelerated by a simple operation, called 'transmigration', which is to import previously generated good solutions (constant-coefficient multipliers) for creating multipliers with different target coefficients. The authors' observation shows that transmigration accelerates a typical evolutionary run by an average of 8.7 times. This implies that the EGG system can acquire and reuse useful subcircuit structures contained in the previously generated multipliers during the evolution process View full abstract»

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  • Linearity analysis and design optimisation for 0.18 μm CMOS RF mixer

    Page(s): 112 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    Equations for the 1dB compression point and third-order intermodulation point as a function of circuit and technology parameters are derived using a Volterra series expansion. The linearity analysis for both single- and double-balanced CMOS Gilbert mixers is examined. The relation between the input third-order intercept point and source inductance is studied in depth. The gate to drain overlap capacitance, which is one of the dominant nonlinear elements in a MOSFET, is included in the model. The design methodology to satisfy the mixer noise figure and conversion gain while optimising linearity is summarized. The analytical predictions are verified with the Cadence SpectreRF circuit simulation and experimental data. Good agreement between the model predictions and experimental data is obtained View full abstract»

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  • Direct-conversion flat-panel X-ray image detectors

    Page(s): 85 - 96
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1389 KB)  

    Flat-panel X-ray image detectors have been shown to be suitable to replace the conventional X-ray film/screen cassettes for medical radiography (static or snapshot imaging). They are capable of capturing the X-ray image digitally immediately after the X-ray exposure which permits a convenient clinical transition to digital radiography. There are two general approaches to the flat-panel X-ray detector technology: direct and indirect conversions. The authors review the operating principles for direct conversion, and formulate and review the required X-ray photoconductor properties for enabling a successful direct conversion detector. Two important photoconductor requirements are discussed in detail, the X-ray sensitivity and dark current, both of which are topical current research areas in seeking the best photoconductor amongst a number of candidate semiconductors such a-Se, PbI2, HgI2 and others. The requirements of medical fluoroscopy (real-time imaging at very low exposure levels) is challenging this technology and demanding even higher X-ray sensitivity View full abstract»

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  • Efficient sampled-data simulation method for transient analysis of nonlinear circuits

    Page(s): 105 - 111
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (631 KB)  

    The paper presents an explicit and efficient transient analysis method for nonlinear circuits. The method makes use of Volterra series representation of nonlinear systems and characterises the behaviour of nonlinear circuits in the time domain using a set of Volterra circuits. The input of the first-order Volterra circuit is the same as that of the nonlinear circuit, whereas that of higher-order Volterra circuits is obtained from the response of lower-order Volterra circuits and interpolation. These Volterra circuits are solved using the sampled-data simulation of linear circuits for computational efficiency and accuracy. The response of the nonlinear circuit is computed at equally spaced instants of time. Numerical results on example circuits demonstrate that the accuracy of the method is comparable to that of widely used predictor-corrector algorithms, but with greatly improved computational efficiency View full abstract»

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  • Optimisation of Reed-Muller PLA implementations

    Page(s): 119 - 128
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1079 KB)  

    Decomposition techniques are utilised for mixed polarity Reed-Muller minimisation, which lead to Reed-Muller programmable logic array implementations for Boolean functions. The proposed algorithm produces a simplified mixed polarity Reed-Muller format from the conventional sum-of-products input based on a top-down strategy. The output format belongs to the most general class of AND/XOR forms, namely exclusive-OR sum-of-products. This method is further generalised to very large multiple output Boolean functions. The developed decomposition method is implemented in the C language and tested with MCNC and IWLS'93 benchmarks. Experimental results show that the decomposition method can produce much better results than Espresso for many test cases. This efficient method offers compact Reed-Muller programmable logic array implementations with the added advantage of easy testability, in contrast to the conventional programmable logic array realisations View full abstract»

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