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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug 2002

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Displaying Results 1 - 25 of 27
  • Determination of material parameters from regions close to the collector using electron beam-induced current

    Page(s): 1455 - 1461
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    The conventional method of extracting the minority carrier diffusion length using the electron beam-induced current (EBIC) technique requires that the electron beam be placed at region more than two diffusion lengths away from the collector. The EBIC signals obtained under this condition usually has low signal to noise ratio. In addition, the true diffusion length of the sample is initially unknown and hence it is difficult to estimate how close the beam can be placed from the collector. To overcome all these difficulties, a new method of extracting minority carrier diffusion length from the EBIC signal is proposed. It is shown that this method can be applied to EBIC signals obtained from regions close to the collector. It is also shown that the surface recombination velocity of the sample can also be obtained using this method. This theory is verified using EBIC data generated from a device simulation software. View full abstract»

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  • Channel noise modeling of deep submicron MOSFETs

    Page(s): 1484 - 1487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 μm CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed. View full abstract»

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  • A simple technique to determine barrier height change in gate oxide caused by electrical stress

    Page(s): 1493 - 1496
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (263 KB) |  | HTML iconHTML  

    Charge trapping in the gate oxide and at the interfaces caused by electrical stress may lead to changes of both the oxide field and the shape of tunneling barrier. In this study, a simple technique based on the analysis of a small change in the Fowler-Nordheim (FN) tunneling current has been developed to quantitatively examine the changes of the effective barrier height and the electric field at the tunneling interface. A power-law dependence of the changes of both the barrier height and the electric field on the stress time is observed. View full abstract»

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  • Determination of channel temperature in AlGaN/GaN HEMTs grown on sapphire and silicon substrates using DC characterization method

    Page(s): 1496 - 1498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (217 KB) |  | HTML iconHTML  

    Self-heating effects and temperature rise in AlGaN/GaN HEMTs grown on silicon and sapphire substrates are studied, exploiting transistor DC characterization methods. A negative differential output resistance is observed for high dissipated power levels. An analytical formula for a source-drain current drop as a function of parasitic source resistance and threshold voltage changes is proposed to explain this behavior. The transistor source resistance and threshold voltage is determined experimentally at different elevated temperatures to construct channel temperature versus dissipated power transfer characteristic. It is found that the HEMT channel temperature increases rapidly with dissipated power and at 6 W/mm reaches values of ∼320°C for sapphire and ∼95°C for silicon substrate, respectively. View full abstract»

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  • Noise margin and leakage in ultra-low leakage SRAM cell design

    Page(s): 1499 - 1501
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB)  

    Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon. View full abstract»

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  • A thermal design methodology for multifinger bipolar transistor structures

    Page(s): 1375 - 1383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    A technique is presented that allows the increase in maximum temperature rise due to thermal coupling in multifinger structures to be predicted for a wide range of finger lengths and spacings by reference to a single, normalized characteristic. Application of this approach to the design of thermal resistance in multifinger structures results in a fast and straightforward method for generating families of structures that meet given power and temperature criteria without thermal simulation-based optimization. The usefulness of this approach is illustrated through solution of a practical design problem, and the accuracy of the method is verified by comparison with the final solutions to numerical simulation. View full abstract»

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  • A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact

    Page(s): 1462 - 1468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB)  

    A novel trench lateral power MOSFET with a trench bottom source contact (TLPM/S) is proposed, fabricated, characterized, and compared with the equivalent TLPM with a trench bottom drain contact (TLPM/D). The TLPM/S is formed along the sidewalls of the trenches so as to reduce the device pitch and realize very small on-resistance per unit area. A total of eight masks are used for fabricating the device. Since the gate electrode and the trench bottom source contact are formed by self-aligning to the trench sidewalls, the device pitch is reduced. Using a line width of 0.6 μm, the fabricated TLPM/S, whose device pitch is 3.0 μm, exhibits a specific on-resistance of 60 mΩ-mm2 for a breakdown voltage of 73 V, which is close to the estimated silicon limit for this voltage class of devices. Due to reduced Miller capacitance, the TLPM/S exhibits excellent switching performance, and is approximately 50% faster than the equivalent TLPM/D. View full abstract»

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  • A micromachined vacuum triode using a carbon nanotube cold cathode

    Page(s): 1478 - 1483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB)  

    A fully integrated on-chip vacuum microtriode using carbon nanotubes as field emitters was constructed laterally on a silicon surface using microelectromechanical systems (MEMS) design and fabrication principles. Each electrode in the triode was made of a hinged polycrystalline silicon panel that could be rotated and locked into an upright position. The device was operated at a current density as high as 16 A/cm2. Although the transconductance was measured only at 1.3 μS, the dc output power delivered at the anode was almost 40 × more than the power lost at the grid electrode. The technique combines high-performance nano-materials with mature solid-state fabrication technology to produce miniaturized power-amplifying vacuum devices in an on-chip form, which could potentially offer a route of integrating vacuum and solid-state electronics and open up new applications for "old-fashioned" vacuum tubes. View full abstract»

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  • An empirical model to determine the grain size of metal-induced lateral crystallized film

    Page(s): 1399 - 1404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (446 KB) |  | HTML iconHTML  

    Thin-film transistors (TFTs) have been fabricated using the nickel-seeded metal-induced lateral crystallization (MILC), in which an amorphous silicon is crystallized to form a large grain polysilicon film. Single crystal SOI, solid phase crystallization (SPC), and MILC TFTs were fabricated and the carrier mobilities extracted. Different types of devices have different variations in electrical properties. An empirical model based on the presence of the grain boundaries is proposed to explain the experimental results. The experimental data was used to extract the model parameters and the number of grains and grain size present in the device channel. The results can be further used to optimize the crystallization process and the device design. View full abstract»

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  • Gyrotron-traveling wave-tube circuits based on lossy ceramics

    Page(s): 1469 - 1477
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB) |  | HTML iconHTML  

    The gyro-traveling wave tube (gyro-TWT) is a microwave amplifier with simultaneous high power, high frequency, and broad bandwidth capabilities. Techniques for providing a controlled loading of the TE01 cylindrical-guide operating mode of a 35 GHz gyro-TWT using monolithic, lossy ceramic structures are presented. The loading scheme, which also suppresses spurious backward-wave oscillations in the TE11, TE21, and TE02 modes, is based on a sequence of alternating ceramic cylindrical shells and metal rings to form the electron beam tunnel. Design techniques for achieving optimal performance and methods for reducing the sensitivity to temperature-induced variations in ceramic dielectric properties are presented. View full abstract»

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  • The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

    Page(s): 1488 - 1490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    Threshold voltage Vt extracted by gm-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance gm and the corresponding gate-to-source voltage Vgs at which peak gm occurs. It ultimately decreases the threshold voltage Vt extracted by the gm-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in gm-maximum extrapolation method. View full abstract»

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  • The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors

    Page(s): 1384 - 1391
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB)  

    High-performance low-voltage thin-film transistors (TFTs) can be fabricated by grain-enhancement methods such as nickel-seeded metal-induced lateral crystallization (MILC). Electrical characteristics of the TFTs may vary due to the existence of the grain boundaries in the device active region. To obtain the best device characteristics, the effect of grain boundaries on the device must be investigated. In this paper, the cumulative distributions of the device properties such as leakage current, threshold voltage, subthreshold slope, and field-effect mobility as a function of different channel lengths and widths were studied. In general, the grain boundary effects decrease with device size. Devices with short channel lengths and wide channel widths may suffer from degradation due to large leakage current. Moreover, the effects due to the location of the nickel-seeding region on device characteristics were investigated. These include the effect of the longitudinal and lateral grain boundaries and the distance between the nickel seeding region and the device. Finally, a design guideline to reduce the grain boundary effect is presented. View full abstract»

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  • InAs/GaAs quantum dot infrared photodetector (QDIP) with double Al0.3Ga0.7As blocking barriers

    Page(s): 1341 - 1347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (313 KB)  

    The ten stacked self-assembled InAs/GaAs quantum dot infrared photodetectors (QDIP) with different Al0.3Ga0.7As barrier widths and growth temperatures were prepared. Asymmetric current-voltage (I-V) characteristics and 2∼7.5 μm detection window were observed. Peak responsivity of 84 mA/W at -0.4 V and peak specific detectivity of 2.5×109 cm-Hz12//W at zero bias were observed at 50 K. The characteristics of polarization insensitivity over the incident light and the high background photocurrent suggest that the self-assembled QDIP can be operated at higher temperature (∼250 K) under normal incidence condition in contrast to quantum well infrared photodetector (QWIP). View full abstract»

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  • Improved string ribbon silicon solar cell performance by rapid thermal firing of screen-printed contacts

    Page(s): 1405 - 1410
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB)  

    Al-enhanced SiNx-induced hydrogenation is implemented to improve the minority carrier lifetime in string ribbon Si. Rapid cooling after the hydrogenation anneal is found to increase the spatially averaged relative lifetime enhancement by over 160% for string ribbon Si samples with a spatially averaged as-grown lifetime of 2.9 μs. Partial coverage of back surface by Al eliminates wafer bowing in 100 μm thick substrates, but reduces the spatially averaged lifetime enhancement to below 100% because vacancy generation at the back surface is decreased. Rapid thermal Firing (RTF) of screen-printed contacts, with high heating and cooling rates, is found to improve string ribbon solar cell efficiency by an average of 1.2% absolute over lamp heated belt furnace contact firing. Light beam-induced current (LBIC) mapping and light biased or differential internal quantum efficiency (IQE) analysis show that the enhancement in cell performance is primarily due to an improved effective diffusion length and diffusion length uniformity, which are both a result of the improved retention of hydrogen at defects achieved during rapid cooling after contact firing. Screen-printed string ribbon cells with independently confirmed efficiencies as high as 14.7% are achieved through an understanding and implementation of hydrogen passivation of defects. View full abstract»

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  • Contrast-enhancement in black dielectric electroluminescent devices

    Page(s): 1348 - 1352
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    A high contrast electroluminescent (EL) device structure is presented. The diffuse luminous reflectivity from the metal/dielectric/phosphor/indium-tin-oxide/glass EL device structure is ∼3%. A Eu-doped GaN phosphor is used to demonstrate the contrast-enhanced operation. Low reflectivity is achieved by inserting a light-absorbing black thick-film BaTiO3 layer between the phosphor and the rear metal electrode. In addition to providing contrast enhancement, the opaque thick dielectric film exhibits capacitance and high voltage reliability (40 nF/cm2, dielectric constant εd ∼ 500-1000, breakdown field Ed,br ∼ 0.1-0.4 MV/cm) similar to that of the highest performance transparent thin-film dielectrics. An EL device luminance of only 20 cd/m2 is sufficient for a display contrast ratio of ∼10:1 under 140 lux indoor ambient lighting (illumination). Under sunlight illumination of 100000 lux, a display contrast ratio of >3:1 is expected with application of additional contrast enhancement techniques. View full abstract»

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  • Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

    Page(s): 1444 - 1454
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (353 KB)  

    Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems. View full abstract»

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  • Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

    Page(s): 1490 - 1492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (247 KB) |  | HTML iconHTML  

    In this work, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10-9 A/μm to 10-12 A/μm. The on/off current ratio is increased by three orders of magnitude accordingly from around 104 to 107. View full abstract»

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  • Micro breakdown in small-area ultrathin gate oxides

    Page(s): 1367 - 1374
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB)  

    The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness tOX=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at VG=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc. View full abstract»

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  • A comparative analysis of substrate current generation mechanisms in tunneling MOS capacitors

    Page(s): 1427 - 1435
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB)  

    This paper presents a critical analysis of the origin of majority and minority carrier substrate currents in tunneling MOS capacitors. For this purpose, a novel, physically-based model, which is comprehensive in terms of impact ionization and hot carrier photon emission and re-absorption in the substrate, is presented. The model provides a better quantitative understanding of the relative importance of different physical mechanisms on the origin of substrate currents in tunneling MOS capacitors featuring different oxide thickness. The results indicate that for thick oxides, the majority carrier substrate current is dominated by anode, hole injection, while the minority carrier current is consistent with a photon emission-absorption mechanism, at least in the range of oxide voltage and oxide thickness covered by the considered experiments. These two currents appear to be strictly correlated because of the relatively flat ratio between impact ionization and photon emission scattering rates and because of the weak dependence of hole transmission probability on oxide thickness and gate bias. Simulations also suggest that, for thinner oxides and smaller oxide voltage drop, the photon emission mechanism might become dominant in the generation of substrate holes. View full abstract»

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  • FinFET design considerations based on 3-D simulation and analytical modeling

    Page(s): 1411 - 1419
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (409 KB) |  | HTML iconHTML  

    Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (Vth) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. Vth roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and Vth roll-off can be included into a universal relation for convenient comparison. View full abstract»

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  • InGaN/GaN light emitting diodes with a p-down structure

    Page(s): 1361 - 1366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (277 KB) |  | HTML iconHTML  

    Nitride-based p-down blue light emitting diodes (LEDs) were successfully fabricated. It was found that we could improve the crystal quality of these nitride-based p-down LEDs by inserting a codoped interlayer between the p-type cladding layer and MQW active layers. It was also found that the turn-on voltage could be reduced from 15 V to less than 5 V for the p-down LED with codoped layer and tunnel layer. The 20 mA output power was 1 mW for the p-down LED with an Mg+Si codoped interlayer and a rough p-tunnel layer. View full abstract»

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  • A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors

    Page(s): 1336 - 1340
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty required for the FET-only circuit. View full abstract»

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  • Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs

    Page(s): 1436 - 1443
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    This work summarizes the results of several experiments to investigate the potential applications of Silicon-Germanium alloy in the fabrication of shallow source/drain (S/D) extension Junctions for deep submicron PMOS transistors. Two approaches were used for the fabrication of p+-Si1-xGex/n-Si heterojunctions. In the first approach, high dose Ge ion implantation followed by boron implantation into Si was used to form very shallow p+-Si1-xGex/n-Si junctions (x≤0.2). In the second approach, thin Ge films were deposited onto Si substrates by conventional low pressure chemical vapor deposition. This was followed by boron implantation into the Ge and thermal annealing to co-diffuse Ge and B atoms into Si and form p+/n heterojunctions. The electrical characteristics of the heterojunction diodes were comparable to those of conventional Si (homo) junctions. Secondary ion mass spectrometry (SIMS) concentration-depth profiles indicate that dopant segregation in the Si1-xGex regions resulted in the formation of ultra-shallow and abrupt junctions that could be used as S/D extensions for sub-100 nm CMOS generations. PMOS transistors fabricated using these techniques exhibit superior short-channel performance compared to control devices, for physical gate lengths down to 60 nm. View full abstract»

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  • Two-dimensional self-consistent simulation of a triangular p-channel SOI nano-flash memory device

    Page(s): 1420 - 1426
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (367 KB)  

    This paper presents the simulation of an SOI nano-flash memory device. The device is composed of a triangular quantum wire channel p-MOSFET with a self-aligned nano-floating gate embedded in the gate oxide. The simulation is carried out by combining TSUPREM-4 and a two-dimensional (2-D) self-consistent solution of the Poisson and Schrodinger equations. The fabrication process as well as quantum physics are taken into account. Hole distribution in the inversion layer of the triangular channel section is calculated in terms of wave functions and energy subbands. The threshold voltage shift between the programming and erasing of the device is investigated. In this paper, we show that the channel shape plays a crucial role in the programming voltage and the threshold voltage shift. Based on the fact that the holes are confined mainly at the top of the triangular channel section, we explain why our triangular channel device can be operated at relatively low programming voltage despite of a thick gate oxide and tunnel oxide. The threshold voltage shift in the triangular channel device is compared with that in a rectangular channel device. The result shows that the triangular channel device exhibits the larger threshold voltage shift. View full abstract»

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  • Surface-free technology by laser annealing (SUFTLA) and its application to poly-Si TFT-LCDs on plastic film with integrated drivers

    Page(s): 1353 - 1360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    In order to realize electronic devices on plastic film, new technology has been developed that enables the transfer of thin-film devices from an original substrate to another substrate by using laser irradiation. This technology was termed SUFTLA, which stands for surface-free technology by laser annealing. A polycrystalline-silicon thin film transistor (poly-Si TFT) back-plane for liquid crystal displays (LCDs) with integrated drivers was fabricated using a low-temperature process (below 425°C) and could be successfully transferred from a glass or quartz substrate to plastic film using this technology. This technology enabled us to fabricate an all-plastic substrate TFT-LCD having a display area of 0.7 in measured diagonally and a pixel count of 428×238. In addition, the operation of the integrated drivers and the displayed image could be confirmed for the first time in the world. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology