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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 4 • Date Apr 2002

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Displaying Results 1 - 8 of 8
  • Speed-power-accuracy tradeoff in high-speed CMOS ADCs

    Page(s): 280 - 287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit View full abstract»

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  • A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

    Page(s): 266 - 272
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency (fc) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a fc of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90°. The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30% View full abstract»

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  • A low-voltage design approach for class AB current-mode circuits

    Page(s): 273 - 279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    An approach for designing analog current-mode circuits with very-low supply voltage requirements is described and applied to the implementation of basic complementary metal-oxide-semiconductor (CMOS) building blocks. The method is based on a biasing circuit exploiting poly resistors and auxiliary differential amplifiers which restricts supply requirements to one threshold voltage plus three saturation voltages. As design examples, a complementary current mirror, a current operational amplifier, and a transconductor are implemented adopting the proposed technique. SPICE simulations using a 0.5-μm process are provided which closely confirm the expected overall good performance of these circuits especially in terms of low-voltage capability and speed View full abstract»

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  • A 1.2-V n-p-n-only integrator for log-domain filtering

    Page(s): 257 - 265
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (345 KB) |  | HTML iconHTML  

    A simple log-domain integrator that operates nominally with a supply voltage of 1.2 V is proposed. It does not employ p-n-p or positive metal-oxide-semiconductor (PMOS) transistors in the signal path. This has two advantages: (1) It makes the integrator suitable for high-frequency applications. (2) The circuit can be implemented using low-cost bipolar processes rather than the more expensive bipolar complementary metal-oxide-semiconductor (BiCMOS) processes or the bipolar processes featuring high-quality p-n-p transistors. A third-order Chebyshev prototype filter, employing the proposed integrator, is realized using a semicustom bipolar array. It consumes 282 μA per pole for a cutoff frequency of 1.5 MHz, achieving a 40.5 dB dynamic range. For lower biasing currents, the circuit can operate from a supply voltage as low as 0.9 V. Detailed experimental results are reported and discussed View full abstract»

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  • A micropower low-distortion digital pulsewidth modulator for a digital class D amplifier

    Page(s): 245 - 256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument class D amplifier. The PWM embodies a novel delta-compensation (δC) sampling process and a novel pulse generator. The δC process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion (THD). Its arithmetic computation is however, substantially simplified. We analytically derive the double Fourier series expression for the δC process and show that the THD is low. The pulse generator is based on a hybrid 9-b counter 3-b tapped-delay-line. We investigate the compromise between the different design parameters that affect its power dissipation and THD. The complete proposed PWM features a simple circuit implementation (small IC area), micropower low voltage operation (~22.1 μW at 1.1 V), low sampling rate (48 kHz) and low harmonic distortion (~0.2%), thereby rendering it suitable for a practical digital hearing instrument. We verify our design by means of computer simulations and on the basis of experimental measurements View full abstract»

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  • An empirical study of minimax-optimal fractional delays for low-pass signals

    Page(s): 288 - 292
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    We consider the design of fractional delay (FD) filters for low-pass signals using the minimax-optimality criterion. In particular, we present an empirically derived relationship between the bandwidth, filter order, delay, and peak error, which is useful for parameter selection in design problems. We also present a simple method for rapid online calculation of FD filters with arbitrary shifts. Finally, we present some numerical results comparing these minimax-optimal FD filters with filters derived via the generalized least squares, Lagrange interpolation, and approximate prolate series windowed methods. The simulations suggest that the minimax-optimal delays are competitive with filters designed by other means, and in some cases can significantly outperform them View full abstract»

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  • Implementation of steerable spatiotemporal image filters on the focal plane

    Page(s): 233 - 244
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chip's architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration, and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low-power consumption at high-computation rates. A 16×16 pixels prototype of the GIP has been fabricated in a standard 1.2-μm CMOS process and its spatiotemporal capabilities have been successfully tested. The chip exhibits 1 GOPS/mW at 20 kft/s while computing four spatiotemporal convolutions in parallel View full abstract»

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  • A novel algorithm for automated optimum design of IIR SC decimators

    Page(s): 293 - 296
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched-capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear programming method is adopted for optimum adjustment of the capacitance values, within a specific decimator structure and a finite number of iterations. Several examples of automatic and optimum design of second-order IIR SC decimators are presented, together with a comparison against previous designs, obtained for the same circuits through the use of traditional methods View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope