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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 4 • Date Apr 2002

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Displaying Results 1 - 8 of 8
  • A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

    Publication Year: 2002 , Page(s): 266 - 272
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-fre... View full abstract»

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  • A 1.2-V n-p-n-only integrator for log-domain filtering

    Publication Year: 2002 , Page(s): 257 - 265
    Cited by:  Papers (12)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (345 KB) |  | HTML iconHTML  

    A simple log-domain integrator that operates nominally with a supply voltage of 1.2 V is proposed. It does not employ p-n-p or positive metal-oxide-semiconductor (PMOS) transistors in the signal path. This has two advantages: (1) It makes the integrator suitable for high-frequency applications. (2) The circuit can be implemented using low-cost bipolar processes rather than the more expensive bipol... View full abstract»

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  • An empirical study of minimax-optimal fractional delays for low-pass signals

    Publication Year: 2002 , Page(s): 288 - 292
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (346 KB) |  | HTML iconHTML  

    We consider the design of fractional delay (FD) filters for low-pass signals using the minimax-optimality criterion. In particular, we present an empirically derived relationship between the bandwidth, filter order, delay, and peak error, which is useful for parameter selection in design problems. We also present a simple method for rapid online calculation of FD filters with arbitrary shifts. Fin... View full abstract»

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  • Speed-power-accuracy tradeoff in high-speed CMOS ADCs

    Publication Year: 2002 , Page(s): 280 - 287
    Cited by:  Papers (54)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scali... View full abstract»

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  • A novel algorithm for automated optimum design of IIR SC decimators

    Publication Year: 2002 , Page(s): 293 - 296
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    This brief presents a novel algorithm for optimizing the design of infinite-impulse response (IIR) switched-capacitor (SC) decimators. It is implemented with a computer-assisted iterative methodology to achieve minimum capacitance spread and usually leading also to the minimization of the total capacitor area, while considering scaling for maximum signal handling capability. A linear/nonlinear pro... View full abstract»

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  • A low-voltage design approach for class AB current-mode circuits

    Publication Year: 2002 , Page(s): 273 - 279
    Cited by:  Papers (15)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    An approach for designing analog current-mode circuits with very-low supply voltage requirements is described and applied to the implementation of basic complementary metal-oxide-semiconductor (CMOS) building blocks. The method is based on a biasing circuit exploiting poly resistors and auxiliary differential amplifiers which restricts supply requirements to one threshold voltage plus three satura... View full abstract»

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  • A micropower low-distortion digital pulsewidth modulator for a digital class D amplifier

    Publication Year: 2002 , Page(s): 245 - 256
    Cited by:  Papers (24)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument class D amplifier. The PWM embodies a novel delta-compensation (δC) sampling process and a novel pulse generator. The δC process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion (THD). Its arithmetic computa... View full abstract»

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  • Implementation of steerable spatiotemporal image filters on the focal plane

    Publication Year: 2002 , Page(s): 233 - 244
    Cited by:  Papers (38)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chip's architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on t... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope