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Solid-State Circuits, IEEE Journal of

Issue 7 • Date July 2002

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Displaying Results 1 - 23 of 23
  • Guest editorial

    Page(s): 795 - 797
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    Freely Available from IEEE
  • 0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability

    Page(s): 932 - 940
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    This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm 2 and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm2 and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment View full abstract»

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  • A robust smart power bandgap reference circuit for use in an automotive environment

    Page(s): 949 - 952
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB) |  | HTML iconHTML  

    In junction-isolated smart power technologies, negative voltages at the drain terminal of a power DMOS lead to minority carrier injection into the substrate. This can cause malfunction of sensitive circuits such as bandgap references and may subsequently lead to severe functional failures of the device. Furthermore, in smart power ICs, very high chip temperatures can occur due to excessive power dissipation on- or off-chip in fault conditions. In such cases, the operation of a bandgap reference must be guaranteed to ensure safe shutdown of the device even at excessive chip temperatures. In this paper, a robust bandgap circuit for the use in smart power ICs is presented. It is insensitive to minority carrier injection into the substrate and operates reliably up to temperatures of 260°C View full abstract»

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  • A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps

    Page(s): 817 - 824
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    The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage ΔΣ modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35-μm CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise+distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage View full abstract»

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  • Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-μm CMOS technology

    Page(s): 953 - 958
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    A novel MOS varactor design is compared to standard MOS varactors and its influence on the tuning range, phase noise, and pushing of a CMOS voltage-controlled oscillator (VCO) for UMTS is presented. Three fully integrated CMOS VCOs have been fabricated in standard 0.25-μm technology, two with different versions of a novel device, and one with a conventional nMOSFET as the tuning element. All of the fully integrated VCOs fulfill UNITS tuning and phase noise specifications with a power consumption of only 7.5 mW at a 2.5-V power supply. The new varactors outperform the nMOSFET by increasing the frequency tuning from ±7% to ±11% or ±13%, while the measured phase noise of all three VCOs is -117 dBc/Hz at a 1 MHz offset from a 4-GHz carrier View full abstract»

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  • A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON

    Page(s): 887 - 894
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    In this paper, we present an integrated 155-Mb/s burst-mode receiver (BMR) for passive optical network (PON) applications. The chip has been designed to receive optical signals over a wide dynamic range (-30 to -8 dBm) and temperature range (-40°C to +85°C). The chip was implemented using a 0.8-μm 35-GHz SiGe BiCMOS technology and occupies an area of 4.3×4.9 mm2 with a power consumption of 500 mW from a supply voltage of 5 V (3.3 V for the digital PECL output). In the receiver analog front end, we used a low-noise wide-band transimpedance amplifier followed by a nonlinear gain stage to cover a wide signal range without changing the transimpedance gain. The circuit dynamically adjusts the receiver threshold voltage through a feedback loop, thus optimizing the pulsewidth distortion and canceling the optical as well as the electrical offset voltages View full abstract»

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  • A fully integrated CMOS receiver front-end for optic Gigabit Ethernet

    Page(s): 874 - 880
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    A fully integrated fiber-optic receiver chip in a CMOS technology is presented. The design was done in a low-cost mixed-signal analog pure CMOS technology with 0.35-μm gate length. It incorporates every building block needed for standard fiber-optic receiver application, e.g., transimpedance amplifier, postamplifier, signal detect, and several control circuits. The chip works without any external components, such as capacitors usually needed to ensure the broadband operation down to several tens of kilohertz. Three designs were processed for typical data applications between 155 Mb/s and 1.25 Gb/s. The difference in the designs can be created by changing only one metal mask and programming some bandwidth and noise-relevant components on the chip. The results in sensitivity, dynamic range, and other behaviors are fully compliant with the relevant standards, such as SONET or IEEE 802.3 (Gigabit Ethernet) and future IEEE 1394 plastic optical fiber (POF) communication View full abstract»

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  • An injection-locking scheme for precision quadrature generation

    Page(s): 845 - 851
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    We describe a novel quadrature splitter based on injection locking a cascade of ring oscillators to a low-phase-noise (external) single-phase reference clock. The output signals are in accurate quadrature with low phase noise over a wide bandwidth. This scheme inherently operates at high signal frequencies and is insensitive to the shape of the reference clock waveform. Experimental results at 2.7 GHz are reported for a prototype implementation in 0.25-μm BiCMOS technology. To prove the viability of this scheme, a single-sideband upconverter was implemented along with the splitter. Over several chips, an average sideband suppression better than 45 dB over a large signal bandwidth of 100 MHz was achieved View full abstract»

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  • A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology

    Page(s): 959 - 962
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    In this paper, we present a fully integrated frequency synthesizer, using an LC voltage-controlled oscillator (LC-VCO) as the core oscillator. The synthesizer is designed to provide various output clock signals for a transceiver chip. Sampling clocks for on-chip analog-to-digital and digital-to-analog conversion modules are also generated, where low jitter is required. The synthesizer also includes an additional digital phase-locked loop and programmable fractional dividers. We present the general concept, special issues related to low jitter, and test chip results. The synthesizer achieves 3-ps rms long-term jitter on a 200-MHz output with 20-mW power and an area of 0.7 mm2 View full abstract»

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  • A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

    Page(s): 904 - 910
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    This paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in 0.8-μm CMOS technology. Although analog implementations have been described in the literature, this decoder is the first to be reported realizing the add-compare-select section entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable digital system. In addition, at 50 Mb/s (the only rate at which comparative data were available), the power consumption per trellis state is similarly about 1/3 that of the best competing analog realization (i.e., excluding, for example, PR4 detectors which use a simplified form of the Viterbi algorithm). The chip contains 3.7 K transistors of which less than 1 K are used in the analog part of the decoder. The die has a core area of 1 mm2, of which about 1/3 contains the analog section. The measured performance is close to that of an ideal Viterbi decoder with infinite quantization. In addition, a technique is described which extends the application of the circuits to decoders with a larger number of states. A typical example is a 64-state decoder for use in high-speed satellite communications View full abstract»

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  • A 80-MHz bandpass ΔΣ modulator for a 100-MHz IF receiver

    Page(s): 798 - 808
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    A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply View full abstract»

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  • A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology

    Page(s): 825 - 834
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    An oversampled digital-to-analog converter (DAC) is presented. The performance of this device has been achieved with a careful tradeoff with power consumption. A digital ΣΔ modulator has been optimized for the 96-dB target. In the switched-capacitor reconstruction filter (SCF), the input structure is embedded in the feedback loop in order to reduce the output noise. The order of the SCF is three, larger than in competitive solutions, allowing to achieve a lower out-of-band noise. Finally, the differential-to-single-ended converter does not strongly limit the overall DAC channel performance. The device has been realized in a standard 3.3-V CMOS technology. With a 28-mW-per-channel power consumption the dynamic range is 98 dB, while the SNDR peak is 86 dB View full abstract»

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  • High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling

    Page(s): 895 - 903
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    In this paper, a 1-Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme is discussed with experimental results for a 0.25-μm CMOS implementation. This chip is the first analog integrated implementation of a reduced state sequence detector. Pipelining and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200-Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 55 mW from a 2.5-V supply. The active area occupies 0.78 mm2. Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other partial-response signaling schemes such as dicode and PR4 View full abstract»

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  • Implementation of scalable power and area efficient high-throughput Viterbi decoders

    Page(s): 941 - 948
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    Today's data reconstruction in digital communication systems requires designs of highest throughput rate at low power. The Viterbi algorithm is a key element in such digital signal processing applications. The nonlinear and recursive nature of the Viterbi decoder makes its high-speed implementation challenging. Several promising approaches to achieve either high throughput or low power have been proposed in the past. A combination of these is developed in this paper. Additional new concepts allow building a signal-flow graph suitable for the design of high-speed Viterbi decoders with low power. Using a flexible datapath generator facilitates the essential quantitative optimization from architectural down to physical level to fully exploit the low-power and high-speed potential of a given technology. With parameterizable design entry, this datapath generator establishes the basis of a scalable platform-based design library. Altogether, this allows coverage of the range of today's industrial interest in high throughput rates, from 150 Msymbols/s up to 1.2 Gsymbols/s using conventional CMOS logic. The features of two exemplary Viterbi decoder implementations prove the benefit of this physically oriented design methodology in terms of speed and low power, when compared to other leading edge implementations View full abstract»

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  • An ADSL-RT full-rate analog front end IC with integrated line driver

    Page(s): 857 - 865
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    An analog front end IC for ADSL systems compliant with ANSI, ITU, and ETSI standards is presented. The IC contains all analog functions on one silicon die, including programmable gain amplifiers, highly linear continuous-time filters, 14-bit DAC and ADC for up to 1.1-MHz signal bandwidth, digitally controlled crystal oscillator, and a line driver capable of delivering +13 dBm to the line. The IC has been fabricated in a mixed-signal 0.6-μm DPTM BiCMOS technology with a chip area of 29 mm2 and a power consumption of only 800 mW, using 3.3-V supply for all blocks, except 12-V supply for the line driver. The high level of integration together with the low power consumption can be considered a benchmark for full-rate ADSL analog front end ICs View full abstract»

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  • A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching

    Page(s): 809 - 816
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    This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz View full abstract»

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  • A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]

    Page(s): 916 - 925
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    The use of magnetic bearings in small biomedical devices poses new challenges for the integration of complex embedded electronic systems. This paper describes a low-power fully integrated two-channel system-on-a-chip (SOC) for two-dimensional (2-D) differential position sensing in magnetic bearings through two pairs of eddy current sensors. It consists of a 312.5 kHz switched-capacitor (SC) sine-wave generator, a two-channel data acquisition unit including a 19-dB quadruple difference instrumentation amplifier, and a demodulating 12-bit ΣΔ analog-to-digital (A/D) converter with DSP-compatible serial interface. A signal-to-noise-plus-distortion ratio (SNDR) of more than 60 dB has been achieved, which corresponds to a resolution of better than 3 μm at a maximum displacement range of 3 mm. The entire system has been integrated in a standard 0.6-μm CMOS technology and consumes 10 mW at a 2.7-V supply View full abstract»

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  • Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system

    Page(s): 881 - 886
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    We propose a novel cell-AGC technique for an ATM-cell-based burst optical receiver on a 156-Mb/s subscriber system. The cell-AGC controls transimpedance gain according to the burst-cell power and enables reception of burst signals with low extinction ratio. In addition, to realize high sensitivity, we developed an amplifier that is stable under changes in ambient conditions and deviations of transistor characteristics on IC. By adopting these techniques in a CMOS preamplifier IC, the detectable power difference between burst cells was enlarged to more than 30 dB, and the minimum sensitivity was improved to less than -39.3 dBm. These performances show that our new IC fully satisfies the high-sensitivity specification of an ATM-PON system, and incorporating this IC in the system makes it more flexible and economical View full abstract»

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  • A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS

    Page(s): 866 - 873
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    An analog front-end (AFE) module designed for use together with a digital cable modem transceiver on one single die is presented. All the analog functionality is implemented in a pure 0.18-μm CMOS process with 1.8-V supply. Besides the critical requirements toward substrate and supply isolation, the design of the high-order antialiasing filter, the high-performance analog-to-digital converter, and the low-jitter phase-locked loop are most challenging. With a silicon area of 9.9 mm 2 and a power dissipation of less than 1 W, this 3-channel AFE can be considered a reference design for first-IF sampling (surface acoustic wave (SAW)-less) cable modem systems View full abstract»

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  • A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800

    Page(s): 835 - 844
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    A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm2. To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints View full abstract»

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  • A 7-GHz 1.8-dB NF CMOS low-noise amplifier

    Page(s): 852 - 856
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    A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-μm CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz View full abstract»

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  • A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature

    Page(s): 926 - 931
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    A high-performance and low-power 32-bit multiply-accumulate unit (MAC) is described in this paper. The last mixed-length encoding scheme used in the MAC leverages the advantage of a 16-bit encoding scheme without adding extra delay to the faster four-stage Wallace tree of a 12-bit encoding scheme. With this new encoding scheme, one-cycle throughput for 16-bit ×16-bit and 32-bit ×16-bit MAC instructions was achieved at very high frequencies. To handle media streams more efficiently, the single-instruction-multiple-data (SIMD) and the multiply-with-implicit-accumulate (MIA) features were added. A mixture of static CMOS logic and complementary pass-gate logic (CPL) was used to achieve the high-speed and low-power goals. Several power-saving techniques were also implemented in this MAC View full abstract»

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  • A 1 K×1 K high dynamic range CMOS image sensor with on-chip programmable region-of-interest readout

    Page(s): 911 - 915
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    An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm2 and the total chip area is 164 mm 2 View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan