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Electron Device Letters, IEEE

Issue 7 • Date July 2002

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Displaying Results 1 - 21 of 21
  • A novel frequency-multiplication device based on three-terminal ballistic junction

    Publication Year: 2002 , Page(s): 377 - 379
    Cited by:  Papers (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (201 KB)  

    In this letter, a novel frequency-multiplication device based on a three-terminal ballistic junction is proposed and demonstrated. A 100 nm-size, three-terminal ballistic junction and a one-dimensional (1D), lateral-field-effect transistor with trench gate-channel insulation are fabricated from high-electron-mobility GaInAs/InP quantum-well material as a single device. The devices show frequency doubling and gain at room temperature. The performance of these devices up to room temperature originates from the nature of the device functionality and the fact that the three-terminal device extensions are maintained below the carrier mean-free path. Furthermore, it is expected that the device performance can be extended up to THz-range. View full abstract»

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  • Oxidation control of GaAs pHEMTs for high efficiency applications

    Publication Year: 2002 , Page(s): 380 - 382
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB) |  | HTML iconHTML  

    In this letter, for the first time, an investigation of partially oxidized GaAs-on-insulator (GOI) AlGaAs/InGaAs/GaAs pseudomorphic HEMTs is reported. Fully oxidized pHEMTs demonstrated minimized substrate leakage current and high output impedance, but suffered from 30/spl sim/40% charge loss. Fully oxidized devices also showed transconductance peaking that could be removed by controlled partial oxidation. Partially oxidized pHEMT devices showed improved power added efficiencies (PAEs) at a low supply voltage of 3.0 V compared to fully oxidized or unoxidized devices and negligible charge loss (<10%). View full abstract»

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  • Physics-based explanation of kink dynamics in AlGaAs/GaAs HFETs

    Publication Year: 2002 , Page(s): 383 - 385
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (211 KB) |  | HTML iconHTML  

    The physical origin of the kink and its dynamics are investigated in AlGaAs/GaAs doped-channel heterostructure field-effect transistors (HFETs) both through measurements and two-dimensional (2D) device simulations. The kink is shown to arise from the interaction of surface deep acceptors with impact-ionization-generated holes, the latter partially discharging the deep levels and therefore leading to conductive-channel widening and to drain-current increase. Under pulsed operation, kink dynamics is governed by hole emission and capture phenomena, prevailing at low and high drain-source voltages, respectively. View full abstract»

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  • Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

    Publication Year: 2002 , Page(s): 386 - 388
    Cited by:  Papers (110)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed. View full abstract»

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  • Improvement of low-temperature gate dielectric formed in N2O plasma by an additional CF4 pretreatment process

    Publication Year: 2002 , Page(s): 389 - 391
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    This study describes a novel technique to form low temperature oxide (<350/spl deg/C). Low-temperature oxides were formed by N/sub 2/O plasma in the plasma-enhanced chemical vapor deposition (PECVD) system with a CF/sub 4/ pretreatment. These oxides demonstrate excellent current-voltage (I-V) characteristics comparable to thermally grown oxides. Experimental results indicate that CF/sub 4/ plasma treatment can significantly improve the reliability of low-temperature oxides. With excellent electrical properties, the technique is highly promising for low-temperature processes. View full abstract»

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  • High-power P-i-N diode with the local lifetime control based on the proximity gettering of platinum

    Publication Year: 2002 , Page(s): 392 - 394
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    We demonstrate for the first time a high-power P-i-N diode with local lifetime control using the proximity gettering of platinum in the FZ silicon. The region of maximal damage resulting from the low-dose helium implantation was decorated by substitutional platinum that diffused from the PtSi anode contact at low temperature (700/spl deg/C) through the P/sup +/-P anode doping at the distance of 70 μm. The diodes show very low forward voltage drop with negative temperature coefficient and very low leakage current even at elevated temperatures while keeping the major advantages of the ion irradiated devices like low turn-off losses and soft recovery. View full abstract»

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  • A high-speed, high-sensitivity silicon lateral trench photodetector

    Publication Year: 2002 , Page(s): 395 - 397
    Cited by:  Papers (20)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias. View full abstract»

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  • A low-voltage CMOS complementary active pixel sensor (CAPS) fabricated using a 0.25 μm CMOS technology

    Publication Year: 2002 , Page(s): 398 - 400
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a VDD below 1 V with a reasonable output swing. View full abstract»

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  • Reduction of the switching time of polymer-dispersed liquid crystal using field oriented addressing

    Publication Year: 2002 , Page(s): 401 - 403
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (211 KB) |  | HTML iconHTML  

    Polymer dispersed liquid crystal (PDLC) is a promising liquid crystal for reflective displays in low power mobile applications. However, it is difficult to obtain full color PDLC displays. Color sequential PDLC is one solution but this requires short PDLC switching times. It is demonstrated that the PDLC switching times can be reduced to color sequential levels by changing the orientation of the electric field (field-oriented addressing). By choosing the right pixel geometry, this can be done at relatively low switching voltages compared to the classic addressing method which is based on changing the magnitude of the electric field. View full abstract»

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  • MOS capacitor on 4H-SiC as a nonvolatile memory element

    Publication Year: 2002 , Page(s): 404 - 406
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB) |  | HTML iconHTML  

    Nonvolatile memory characteristics of MOS capacitors are presented in this letter. The MOS capacitors have been fabricated on N-type 4H SiC substrate with nitrided oxide-semiconductor interface. The charge-retention time is in the order of 4.6/spl times/10/sup 9/ years, as determined by thermally activated (275-355/spl deg/C) capacitance-transient measurements and extrapolation to room temperature. The estimated activation energy of the charge-generation processes is 1.6 eV. The results and the analysis presented in this letter demonstrate that 4H SiC MOS capacitors can be used as a memory element in nonvolatile RAMs. View full abstract»

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  • Development of high-performance polycrystalline silicon thin-film transistors (TFTs) using defect control process technologies

    Publication Year: 2002 , Page(s): 407 - 409
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425/spl deg/C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO/sub 2//Si interface were controlled by a gate SiO/sub 2/ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm/sup 2/V/sup -1/s/sup -1/, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics. View full abstract»

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  • Effects of wet N/sub 2/O oxidation on interface properties of 6H-SiC MOS capacitors

    Publication Year: 2002 , Page(s): 410 - 412
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    Oxynitrides were grown on n- and p-type 6H-SiC by wet N/sub 2/O oxidation (bubbling N/sub 2/O gas through deionized water at 95/spl deg/C) or dry N/sub 2/O oxidation followed by wet N/sub 2/O oxidation. Their oxide/SiC interfaces were investigated for fresh and stressed devices. It was found that both processes improve p-SiC/oxide but deteriorate n-SiC/oxide interface properties when compared to dry N/sub 2/O oxidation alone. The involved mechanism could be enhanced removal of unwanted carbon compounds near the interface due to the wet ambient, and hence a reduction of donor-like interface states for the p-type devices. As for the n-type devices, incorporation of hydrogen-related species near the interface under the wet ambient increases acceptor-like interface states. In summary, wet N/sub 2/O oxidation can be used for providing comparable reliability for nand p-SiC MOS devices, and especially for obtaining high-quality oxide-SiC interfaces in p-type MOS devices. View full abstract»

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  • A new lateral anode switched thyristor (LAST) with current saturation and low turn-off time

    Publication Year: 2002 , Page(s): 413 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB) |  | HTML iconHTML  

    A novel MOS-gate controlled thyristor, entitled lateral anode switched thyristor (LAST), which exhibits a high current saturation and a low turn-off time, is proposed and successfully fabricated. Experimental results show that the new LAST achieves a current saturation capability larger than 1200 A/cm2 even at high anode voltages. The forward voltage drop of LAST is 1.2 V at 100 A/cm2 where 10 V was biased to the dual gates. The turn-off time of LAST without any lifetime-control process is 1.5 μs while that of LAST without p/sup +/ diverter is about 2.9 μs. Our experimental data indicates that the p/sup +/ diverter successfully diverts holes in the drift region during the turn-off and a turn-off time is considerably decreased in the proposed LAST. The LAST, where any trouble-some parasitic thyristor mechanism is eliminated, completely suppresses a latch-up and increases the maximum controllable current considerably. View full abstract»

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  • Comparison of electrical and reliability characteristics of different 14 /spl Aring/ oxynitride gate dielectrics

    Publication Year: 2002 , Page(s): 416 - 418
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    A comparison of RTNO, N/sub 2/O and N/sub 2/O-ISSG ultrathin oxynitride gate dielectrics fabricated by combining a remote plasma nitridation (RPN) treatment with equal physical oxide thickness of 14 /spl Aring/ is explored. The N/sub 2/O-ISSG oxynitride gate dielectric film demonstrates good interface properties, higher mobility and excellent reliability. This film by RPN treatment is thus attractive as the gate dielectric for future ultra-large scale integration (ULSI) devices. View full abstract»

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  • Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs

    Publication Year: 2002 , Page(s): 419 - 421
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    We have proposed and simulated a new 10-nm and sub-10 nm n-MOSFET that has a recessed channel and asymmetric source/drain Schottky Contacts (RASC MOSFETs). The recessed channel can effectively suppress short-channel effects, and the asymmetric source/drain contacts in which a higher Schottky barrier at the source contact can yield smaller off-state current while a lower Schottky barrier at the drain can yield larger on-state current. The simulated results show that the device can exhibit an on/off ratio as high as 106 and an on-state current of 393 μA/μm with a supply voltage of 1.0 V. Furthermore, the parameters of RASC MOSFETs are rather insensitive to size variations. These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications. View full abstract»

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  • A new process-variation-immunity method for extracting capacitance coupling coefficients in flash memory cells

    Publication Year: 2002 , Page(s): 422 - 424
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I/sub D/=I/sub 0/ exp[q(V/sub GB/ - nV/sub SB/)/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients. View full abstract»

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  • Temperature dependence of hot-carrier-induced degradation in 0.1 μm SOI nMOSFETs with thin oxide

    Publication Year: 2002 , Page(s): 425 - 427
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect. View full abstract»

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  • Normalized mutual integral difference method to extract threshold voltage of MOSFETs

    Publication Year: 2002 , Page(s): 428 - 430
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    A novel normalized mutual integral difference (NMID) method is presented in this letter to extract the threshold voltage of MOSFETs. The basic principle of this method is to utilize the exponential-linear characteristics of MOSFETs current so as to obtain the normalized mutual integral difference extreme spectral characteristics. The proposed method is sensitive to channel length variation while being insensitive to parasitic resistance. The extracted results on the threshold voltage show a good consistency and have been compared with those obtained by the second-derivative technique. A good correlation between both methods has also been found. View full abstract»

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  • Roughness-enhanced reliability of MOS tunneling diodes

    Publication Year: 2002 , Page(s): 431 - 433
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    Both electrical and optical reliabilities of PMOS and NMOS tunneling diodes are enhanced by oxide roughness, prepared by very high vacuum prebake technology. For rough PMOS devices, as compared to flat PMOS devices, the Weibull plot of T/sub BD/ shows a 2.5-fold enhancement at 63% failure rate, while both the D/sub 2/ and H/sub 2/-treated flat PMOS devices show similar inferior reliability. For rough NMOS devices, as compared to flat NMOS devices, the Weibull plot of T/sub BD/ shows a 4.9-fold enhancement at 63% failure rate. The time evolutions of the light emission from rough PMOS and NMOS diodes degrade much less than those of flat PMOS and NMOS diodes. The momentum reduction perpendicular to the Si/SiO/sub 2/ interface by roughness scattering could possibly make it difficult to form defects in the bulk oxide and at the Si/SiO/sub 2/ interface by the impact of the energetic electrons and holes. View full abstract»

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  • A simple and accurate method for extracting substrate resistance of RF MOSFETs

    Publication Year: 2002 , Page(s): 434 - 436
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    In this paper, a simple and accurate method was proposed for extracting substrate resistance of an RF MOSFET, the substrate of which is represented by a single resistor. The extraction results from the measured network parameters are presented for various bias conditions. Excellent agreement between the results of measurements and the model for the extracted substrate resistance was obtained up to 18 GHz. Also, the resistance extracted using the proposed method was shown to give scalable results. View full abstract»

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  • Correction to "A novel 3-D BiCMOS technology using selective epitaxy growth (SEG) and lateral solid phase epitaxial (LSPE)"

    Publication Year: 2002 , Page(s): 437
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (154 KB)  

    First Page of the Article
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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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