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IEEE Transactions on Computers

Issue 5 • Date May 2002

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Displaying Results 1 - 13 of 13
  • Equally spaced polynomials, dual bases, and multiplication in F(2 n)

    Publication Year: 2002, Page(s):588 - 591
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    A proposed multiplier for finite fields given by equally spaced polynomials is based on the transformation from the polynomial basis to its dual basis, combined with multiplication by a constant. We classify the constants that are optimal regarding the cost of this operation and investigate the cost of the inverse transformation View full abstract»

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  • Efficient tests for realistic faults in dual-port SRAMs

    Publication Year: 2002, Page(s):460 - 473
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB) | HTML iconHTML

    This paper begins with an overview of realistic fault models for dual-port memories, divided into single-port faults and faults unique for dual-port memories. The latter faults cannot be detected with conventional single-port memory tests; they require special tests. A precise notation for all faults, such that ambiguities and misunderstandings are prevented, has been emphasized. Next, the paper p... View full abstract»

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  • Streaming BDD manipulation

    Publication Year: 2002, Page(s):474 - 485
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB) | HTML iconHTML

    Binary decision diagrams (BDDs) are commonly used for handling Boolean functions because of their excellent efficiency in terms of time and space. However, the conventional BDD manipulation algorithm is strongly based on the hash table technique, so it always encounters the memory overflow problem when handling large-scale BDD data. This paper proposes a new streaming BDD manipulation method that ... View full abstract»

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  • Examining smart-card security under the threat of power analysis attacks

    Publication Year: 2002, Page(s):541 - 552
    Cited by:  Papers (274)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    This paper examines how monitoring power consumption signals might breach smart-card security. Both simple power analysis and differential power analysis attacks are investigated. The theory behind these attacks is reviewed. Then, we concentrate on showing how power analysis theory can be applied to attack an actual smart card. We examine the noise characteristics of the power signals and develop ... View full abstract»

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  • A method for compressing test data based on Burrows-Wheeler transformation

    Publication Year: 2002, Page(s):486 - 497
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    The overall throughput of automatic test equipment (ATE) is affected by the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper, we propose a new test data compression method that aims to fully utilize... View full abstract»

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  • On the quality of service of failure detectors

    Publication Year: 2002, Page(s):561 - 580
    Cited by:  Papers (98)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB) | HTML iconHTML

    We study the quality of service (QoS) of failure detectors. By QoS, we mean a specification that quantifies 1) how fast the failure detector detects actual failures and 2) how well it avoids false detections. We first propose a set of QoS metrics to specify failure detectors for systems with probabilistic behaviors, i.e., for systems where message delays and message losses follow some probability ... View full abstract»

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  • On finding feasible solutions for the delay constrained group multicast routing problem

    Publication Year: 2002, Page(s):581 - 588
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (431 KB) | HTML iconHTML

    Group multicasting is a generalization of multicasting whereby every member of a group is allowed to multicast messages to other members that belong to the same group. In this paper, we study the problem of finding feasible solutions for the delay constrained group multicast routing problem (DCGMRP). The routing problem in this case involves the construction of a set of delay bounded multicast tre... View full abstract»

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  • Test bus sizing for system-on-a-chip

    Publication Year: 2002, Page(s):449 - 459
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    System-on-a-chip (SOC) designs present a number of unique testability challenges to system integrators. Test access to embedded cores often requires dedicated test access mechanisms (TAMs). We present an improved approach for designing efficient TAMs and investigate the problems of improved deserialization of test data in the core wrapper, optimal test bus sizing, and optimal assignment of cores t... View full abstract»

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  • Locally subcube-connected hypercube networks: theoretical analysis and experimental results

    Publication Year: 2002, Page(s):530 - 540
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (705 KB) | HTML iconHTML

    We study hypercube networks with a very large number of faulty nodes. A simple and natural condition, the local subcube-connectivity, is identified under which hypercube networks with a very large number of faulty nodes still remain connected. The condition of local subcube-connectivity can be detected and maintained in a distributed manner based on localized management. Efficient routing algorith... View full abstract»

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  • Fault-tolerant meshes with small degree

    Publication Year: 2002, Page(s):553 - 560
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    In this paper, we study the design of fault-tolerant networks for arrays and meshes by adding redundant nodes and edges. For a target graph G (linear array or mesh in this paper), a graph G' is called a k-fault-tolerant graph of G if when we remove any k nodes from G', it still contains a subgraph isomorphic to G. The major quality measures for a fault-tolerant graph are the number of spare nodes ... View full abstract»

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  • A new construction of Massey-Omura parallel multiplier over GF(2 m)

    Publication Year: 2002, Page(s):511 - 520
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB) | HTML iconHTML

    The Massey-Omura multiplier of GF(2m) uses a normal basis and its bit parallel version is usually implemented using m identical combinational logic blocks whose inputs are cyclically shifted from one another. In the past, it was shown that, for a class of finite fields defined by irreducible all-one polynomials, the parallel Massey-Omura multiplier had redundancy and a modified architec... View full abstract»

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  • Montgomery multiplier and squarer for a class of finite fields

    Publication Year: 2002, Page(s):521 - 529
    Cited by:  Papers (31)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB) | HTML iconHTML

    Montgomery multiplication in GF(2m) is defined by a(x)b(x)r-1(x) mod f(x), where the field is generated by a root of the irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2m), and r(x) is a fixed field element in GF(2 m). In this paper, first, a slightly generalized Montgomery multiplication algorithm in GF(2m) is present... View full abstract»

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  • A design diversity metric and analysis of redundant systems

    Publication Year: 2002, Page(s):498 - 510
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (611 KB) | HTML iconHTML

    Redundant systems are designed using multiple copies of the same resource (e.g., a logic network or a software module) in order to increase system dependability. Design diversity has long been used to protect redundant systems from common-mode failures. The conventional notion of diversity relies on "independent" generation of "different" implementations. This concept is qualitative and does not p... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org