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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2002

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Displaying Results 1 - 25 of 27
  • Changes in the Editorial Board

    Publication Year: 2002 , Page(s): 957
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  • Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates

    Publication Year: 2002 , Page(s): 1027 - 1033
    Cited by:  Papers (33)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design View full abstract»

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  • A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for nonsaturating VLSI logic design

    Publication Year: 2002 , Page(s): 1070 - 1072
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    The novel characteristics of a new lateral PNM Schottky collector bipolar transistor (SCBT) on silicon-on-insulator (SOI) are explored using two-dimensional (2D) simulation. The collector-base junction of the proposed lateral PNM transistor consists of a Schottky junction between n-base (N) and metal (M). The characteristics of this structure are compared with that of lateral PNP transistors on SOI. We demonstrate that the proposed structure has a superior performance in terms of reduced collector resistance, high current gain, negligible base widening, and very low reverse recovery time compared to the compatible lateral PNP transistors. A simple fabrication procedure is also suggested providing the incentive for experimental verification View full abstract»

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  • Active-matrix organic light-emitting diode displays realized using metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors

    Publication Year: 2002 , Page(s): 991 - 996
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (337 KB)  

    Requirement on thin-film transistors, particularly in terms of current-drive and parameter uniformity, for active-matrix organic light-emitting diode displays, was analyzed. Metal-induced unilaterally crystallized polycrystalline silicon thin-film transistor technology was shown to satisfy such and other demands. Though pixel designs involving more transistors were certainly advantageous, appropriate biasing scheme allowed a simpler and larger aperture-ratio two-transistor design. As a demonstration, active matrices were fabricated and integrated with organic light-emitting diodes to make monochrome video display panels, each consisting of 120 rows and 160 columns View full abstract»

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  • A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs

    Publication Year: 2002 , Page(s): 1086 - 1090
    Cited by:  Papers (62)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (317 KB) |  | HTML iconHTML  

    A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N A) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement View full abstract»

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  • Improvement of RCA transistor using RTA annealing after the formation of interfacial oxide

    Publication Year: 2002 , Page(s): 1075 - 1076
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (175 KB) |  | HTML iconHTML  

    A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 × 8 μm2. The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively View full abstract»

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  • A novel geometry for circular series connected multilevel inductors for CMOS RF integrated circuits

    Publication Year: 2002 , Page(s): 1084 - 1086
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    The scope of this brief is to introduce a novel geometry for circular series connected multilevel inductors. The idea is to improve the overlapping of the different metal layers that form the integrated inductor to maximize the magnetic flux shared by them and so the inductance. The performance of this new geometry has been compared with the conventional one, using Agilent HFSS field solver. After that, two multilevel inductors using this new geometry have been fabricated in a standard 0.6 μm three-metal CMOS process and measured View full abstract»

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  • Analysis of the electrical breakdown in hydrogenated amorphous silicon thin-film transistors

    Publication Year: 2002 , Page(s): 1012 - 1018
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (391 KB) |  | HTML iconHTML  

    Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to 1 μs) shows a clear dependence on the channel length. A hypothesis that electrical breakdown in the case of short channel TFTs is due to the punch-through is built on this dependence and is proved by means of electrical simulations. Further, the presence of avalanche breakdown in amorphous silicon thin-film transistors is simulated and confirmed. It is finally assumed that the breakdown is a thermal process. Three-dimensional (3-D) electrothermal simulations are performed in the static and transient regime, confirming the location of the breakdown spot within the TFT from the electrical simulations and postbreakdown observations View full abstract»

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  • Emission current enhancement of MIM cathodes by optimizing the tunneling insulator thickness

    Publication Year: 2002 , Page(s): 1059 - 1065
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (302 KB) |  | HTML iconHTML  

    The relationship between the thickness of the anodized Al2 O3 tunneling insulator and the transfer ratio was investigated for metal-insulator-metal (MIM) cathodes to optimize the thickness in terms of a high transfer ratio and emission current. Combining ellipsometry, X-ray photoelectron spectroscopy (XPS), and transmission electron microscopy (TEM), we determined the accurate thickness of an anodized Al film less than 20 nm-thick. With the knowledge of accurate thickness, we found that the transfer ratio increases as the insulator thickness increases from 5.2 nm to 10.6 nm, but saturates at 13.3 nm and decreases slightly at 20.1 nm. Optimizing the thickness of the insulator to 13.3 nm raised the transfer ratio of 0.1% for our previous work (Kusunoki and Suzuki, IEEE Trans. Electron Devices, vol. 47, pp. 1667-1672, 2000) to 0.7%. A high emission current of 14 mA/cm2 was thus obtained. The existence of an optimal thickness for the anodized Al2O3 insulator was also clarified from a theoretical simulation. This is the result of a trade-off, as thickness increases, between the decreasing probability of cut-off at the surface workfunction barrier of the Ir-Pt-Au top electrode and the increased scattering of hot electrons inside the Al 2O3 insulator and top electrode. The relationship is discussed on the basis of the absolute distribution of energy of the hot electrons, which we determined by simulating inelastic scattering driven by electron-optical phonon interaction in the Al2O3 insulator View full abstract»

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  • Analysis and design of a low-voltage high-frequency LDMOS transistor

    Publication Year: 2002 , Page(s): 976 - 980
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    For a low voltage lateral double-diffused MOS (LDMOS) transistor, the output performance has been improved in terms of fMAX. This is done by decreasing the output capacitance and thus decreasing the total output conductance. Extraction of the model parameters has been made and the most efficient parameter to improve was identified and linked to a specific part of the transistor structure. Layout changes in the n-well/p-base region were done as the result of the model analyses and finally, the modified devices were processed. Measurements on the improved devices showed results that closely, matched the expected, and fMAX was increased with 30% and only a slight decrease in f T. Finally, the capacitance reduction in the n-well/p-base junction was measured by direct. measurements View full abstract»

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  • Photodetectors monolithically integrated on SOI substrate for optical pickup using blue or near-infrared semiconductor laser

    Publication Year: 2002 , Page(s): 997 - 1004
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    We made photodetectors on a silicon-on-insulator (SOI) substrate by a 0.35-μm BiCMOS fabrication process to detect the signal light used in an optical disk system. Investigating their characteristics at two wavelengths, 410 and 780 nm, for different structures, we found that the thickness of the silicon crystalline layer on the insulator strongly affected the frequency response at the longer wavelength, while the cutoff frequency was over 500 MHz for the shorter wavelength. We also simulated the frequency response View full abstract»

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  • Ultrathin gate oxide reliability: physical models, statistics, and characterization

    Publication Year: 2002 , Page(s): 958 - 971
    Cited by:  Papers (50)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB) |  | HTML iconHTML  

    The present understanding of wear-out and breakdown in ultrathin (tox < 5.0 nm) SiO2 gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed View full abstract»

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  • Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

    Publication Year: 2002 , Page(s): 1077 - 1079
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle VT adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes View full abstract»

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  • Realization of a resonant tunneling permeable base transistor with optimized overgrown GaAs interfaces

    Publication Year: 2002 , Page(s): 1066 - 1069
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB)  

    A resonant tunneling permeable base transistor has been realized experimentally by overgrowing a tungsten grating placed in direct vicinity to a double barrier heterostructure. In this way, we can directly modulate the tunneling current via an embedded gate. Since the quality of the overgrown interface is critical, special attention is paid to this issue, and the effect of different wet etchants prior to overgrowth is studied both by electrical measurements and by the use of an atomic force microscope. A clear dependence of the electrical properties and the crystal quality on the etchants used is found. This is a key result for the realization of our resonant tunneling device View full abstract»

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  • Third-order intermodulation reduction by harmonic injection in a TWT amplifier

    Publication Year: 2002 , Page(s): 1082 - 1084
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A method for reducing the two-tone third-order intermodulation products arising from two carrier frequencies at 1.95 and 2.00 GHz is demonstrated in a traveling wave tube-distributed amplifier. The optimum amplitude and phase of an injected second harmonic and the resulting intermodulation suppression of up to 24.2 dB are examined for fundamental drive levels approaching saturation View full abstract»

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  • Field-emission display based on nonformed MIM-cathode array

    Publication Year: 2002 , Page(s): 1005 - 1011
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    We developed nonformed metal-insulator-metal (MIM) cathodes and demonstrated their suitability for field-emission displays (FEDs). The MIM cathodes have an emission current density of 5.8 mA/cm2 at an operation voltage of 9 V. The cathodes are operated in the nonformed state, and they exhibit no fluctuation in the emission current, even without a ballast resistor. At a cathode-anode separation of 2 mm and an acceleration voltage of 4 kV, the divergence of the emitted electron beam is 25 μm. These features make nonformed MIM cathodes suitable for high-voltage acceleration-type FEDs. We also fabricated a prototype 3.8-cm diagonal frit-sealed color display, and demonstrated its matrix-multiplexing operation View full abstract»

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  • On the applicability of nonself-consistent Monte Carlo device simulations

    Publication Year: 2002 , Page(s): 1072 - 1074
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB) |  | HTML iconHTML  

    Recently, nonself-consistent (with respect to the electric field) Monte Carlo (NSC-MC) simulations have been proposed for the estimation of the noise and expected value of stationary terminal currents without examining the accuracy of the NSC approximation for these kinds of simulations. Comparison with self-consistent (SC) simulations reveals that NSC simulations of quantities like the drain current of a MOSFET or collector current of a BJT tend to reproduce the results of the momentum-based model used to calculate the electric field without improving the accuracy. In case of terminal current noise it is found that under nonequilibrium conditions the NSC results can substantially overestimate the SC results View full abstract»

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  • High-voltage (3 kV) UMOSFETs in 4H-SiC

    Publication Year: 2002 , Page(s): 972 - 975
    Cited by:  Papers (6)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    Vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) in 4H-SiC having both trench oxide protection and junction termination extension (JTE) are reported for the first time. Devices are fabricated with and without counter-doped channels. Blocking voltages and specific on-resistances are 3360 V and 199 mΩ-cm2 for doped-channel FETs and 3055 V and 121 mΩ-cm2 for FETs without doped channels. These blocking voltages are the highest reported to date for UMOSFETs in SiC View full abstract»

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  • Leakage scaling in deep submicron CMOS for SoC

    Publication Year: 2002 , Page(s): 1034 - 1041
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (347 KB) |  | HTML iconHTML  

    In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (Ioff ) (i.e. subthreshold leakage (Isub), gate edge-direct-tunneling leakage (IEDT), gate-induced drain-leakage (IGIDL), and bulk band-to-band-tunneling leakage (IB-BTBT)). In addition, the high temperature characteristics of Ioff with reverse body bias (VB) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum VB, which minimizes Ioff, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control IB-BTBT and IGIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (IG-on) and IEDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (ISB) is also analyzed View full abstract»

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  • Influences of buried-oxide interface on inversion-layer mobility in ultra-thin SOI MOSFETs

    Publication Year: 2002 , Page(s): 1042 - 1048
    Cited by:  Papers (31)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This paper reports on a study of the inversion-layer mobility in n-channel Si MOSFETs fabricated on a silicon-on-insulator (SOI) substrate. In order to make clear the influences of the buried-oxide interface on the inversion-layer mobility in ultra-thin film SOI transistors, SOI wafers of different quality at the buried-oxide interface were prepared, and the mobility behaviors were compared quantitatively. The transistors with a relatively thick SOI film exhibited the universal relationship between the effective mobility and the effective normal field, regardless of the buried-oxide interface quality. It was found, however, that Coulomb scattering due to charged centers at the backside interface between SOI films and buried oxides has great influence on the effective mobility in the thin SOI thickness region, depending on the buried-oxide interface quality. This means that Coulomb scattering due to charged centers at the buried-oxide interface can degrade the mobility with decreasing SOI thickness, unless the SOI wafer quality at the buried-oxide interface is controlled carefully View full abstract»

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  • Impact of strong quantum confinement on the performance of a highly asymmetric device structure: Monte Carlo particle-based simulation of a focused-ion-beam MOSFET

    Publication Year: 2002 , Page(s): 1019 - 1026
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (321 KB) |  | HTML iconHTML  

    A highly asymmetric 250 nm n-channel MOSFET, with a 70-nm p+ -implant placed at the source end of the channel (achievable by focused-ion-beam (FIB) implantation, so the device is named FIBMOS), has been simulated using a two-dimensional (2-D) coupled Monte Carlo-Poisson solver, in which quantum confinement effects have been taken into account by incorporating an effective potential scheme into the particle simulator. Although the device is a long-channel one, its performance is dictated by the highly doped p+-implant at the source end of the channel, and it is crucial to properly account for the quantum-confinement effects in transport, especially at the implant/oxide interface. We show that parameters such as threshold voltage and device transconductance are extremely sensitive to the proper treatment of quantization effects. On the other hand, the built-in electric field, due to the pronounced asymmetry caused by the presence of the p+-implant, drastically influences the carrier transport, and consequently, the device output characteristics, in particular the magnitude of the velocity overshoot effect and the low-field electron mobility View full abstract»

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  • Pyramid-shaped silicon photodetector with subwavelength aperture [for NSOM]

    Publication Year: 2002 , Page(s): 986 - 990
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (221 KB) |  | HTML iconHTML  

    We present a new type of silicon photodetector with a subwavelength aperture designed to scan material surfaces with a resolution inaccessible by conventional optical microscopy. Such a probe is designed for integration into a near-field scanning optical microscope (NSOM) for scanning and collecting information from the near-field region located at the vicinity of the surface. The photodetector, which was realized by conventional microelectronics technology, is located on top of a 250-μm-high pyramid, enabling detection of reflected as well as transmitted light. The light sensitive part of the probe consists of a micromachined silicon structure built using anisotropic etch solutions such as ethylene diamine pyrocatechol (EDP) and KOH. The shape of the probe is a truncated double pyramid with a ring shape top silicon/aluminum Schottky diode surrounding an exposed silicon photosensitive area of about 150 nm in diameter. Typical I-V characteristics and optical response measurements are presented View full abstract»

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  • Experimental and theoretical analysis of energy capability of RESURF LDMOSFETs and its correlation with static electrical safe operating area (SOA)

    Publication Year: 2002 , Page(s): 1049 - 1058
    Cited by:  Papers (14)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    Thermal and electrical destruction of 55 V single and double reduced surface field (RESURF) lateral double-diffused MOSFETs (LDMOSFETs) in smart power ICs are investigated by experiments, simulations, and theoretical modeling. Static safe operating area (SOA) and single pulse dynamic SOA (energy capability) have been studied and correlated. Single RESURF device failure and hence the energy capability is controlled by electrical phenomenon for drain to source voltage near breakdown voltages, whereas the energy capability of the double RESURF device is shown to be controlled by thermal phenomenon for voltage ranges up to about 5 V below the breakdown voltage. Measured energy capability data have been used to obtain critical temperatures for device failure, which decreases with an increase in drain to source voltage. We have empirically shown using experimental data that if the dynamic SOA of the device comes within about 2-5× of the static SOA boundary, the device failure is strongly influenced by avalanche multiplication. An analytical model based on Green's function formulation is derived and proposed which can predict energy capability of LDMOSFETs for a wide range of device geometry. The calculated data show excellent matching with the measurements and are within ±10%. A new technique of distributing power within a device by applying less power at the center and more at the edges is proposed, which realizes significant improvement in energy capability by optimizing the temperature distribution within the device View full abstract»

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  • New collector undercut technique using a SiN sidewall for low base contact resistance in InP/InGaAs SHBTs

    Publication Year: 2002 , Page(s): 1079 - 1082
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    A new collector undercut process using SiN protection sidewall has been developed for high speed InP/InGaAs single heterojunction bipolar transistors (HBTs). The HBTs fabricated using the technique have a larger base contact area, resulting in a smaller DC current gain and smaller base contact resistance than HBTs fabricated using a conventional undercut process while maintaining low Cbc. Due to the reduced base contact resistance, the maximum oscillation frequency (fmax) has been enhanced from 162 GHz to 208 GHz. This result clearly shows the effectiveness of this technique for high-speed HBT process, especially for the HBTs with a thick collector layer, and narrow base metal width View full abstract»

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  • InGaN/GaN tunnel-injection blue light-emitting diodes

    Publication Year: 2002 , Page(s): 1093 - 1095
    Cited by:  Papers (28)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    A charge asymmetric resonance tunneling (CART) structure was applied to nitride-based blue light emitting diodes (LEDs) to enhance their output efficiency. It was found that with a 20-nm-thick In0.18Ga0.82N electron emitter layer, we could increase the LED output intensity from 28.3 minicandela (mcd) to 43.2 mcd (i.e., a 53% increase). However, a further increase in electron emitter layer thickness will reduce the intensity due to relaxation. It was also found that we could decrease the 20 mA forward voltage from 4.16 V to 3.58 V with a proper electron emitter layer View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego