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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 1 • Date Jan. 2002

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Displaying Results 1 - 10 of 10
  • Editorial

    Publication Year: 2002 , Page(s): 2
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  • Abstracts

    Publication Year: 2002 , Page(s): 3 - 4
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  • Fine-line conductor manufacturing using drop-on demand PZT printing technology

    Publication Year: 2002 , Page(s): 26 - 33
    Cited by:  Papers (57)  |  Patents (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (430 KB) |  | HTML iconHTML  

    An emerging selective metallization process to fabricate fine-line conductors based on drop-on-demand (DOD) ink jet printing and novel nano-particle fluid suspensions (NPFS) was studied. The suspensions consist of 1-10 nm silver or gold particulates that are homogeneously suspended in an organic carrier. A piezo-electric droplet generator driven by a bipolar voltage signal is used to dispense 50-70 μm diameter droplets traveling at 1-3 m/s before impacting a compliant polyimide substrate. The deposit/substrate composite is subsequently processed at 300°C for 15 min to allow for complete evaporation of the carrier and for sintering of the nano-particles, thereby yielding a finished circuit interconnect. Test vehicles created using this technique exhibit features as fine as 120 μm wide and 1 μm thick with resistivities on the order of 3.5×10-5 Ωcm. The circuitry performed well under environmental conditioning. As expected, repeatability of circuitry fabrication showed sensitivity to the generation of steady, satellite-free droplets. In an effort to generate droplets consistently, it is essential to develop a strong fundamental understanding of the correlation between device excitation parameters and dispensed fluid properties, and to resolve the microrheological behavior of the NPFS when flowing through the droplet generator View full abstract»

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  • Modeling and analysis of 3-D solenoid embedded inductors

    Publication Year: 2002 , Page(s): 34 - 41
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (379 KB) |  | HTML iconHTML  

    Investigation of the statistical variation of integrated passive components is crucial for designing and characterizing the performance of multichip module (MCM) substrates. In this paper, the statistical analysis of three-dimensional (3-D) solenoid inductors manufactured in a multilayer low-temperature cofired ceramic (LTCC) process is presented. A set of integrated inductor structures is fabricated, and their scattering parameters are measured for a range of frequencies from 50 MHz to 5 GHz. Using optimized equivalent circuits obtained from HSPICE, mean and absolute deviation is calculated for each component of each device model. Monte Carlo Analysis for the inductor structures is then performed using HSPICE. Using a comparison of the Monte Carlo results and measured data, it is determined that for even a small number of sample structures, the statistical variation of the component values provides an accurate representation of the overall inductor performance View full abstract»

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  • Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

    Publication Year: 2002 , Page(s): 42 - 50
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB) |  | HTML iconHTML  

    Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study View full abstract»

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  • Complex ceramic-polymer composite microparts made by microstereolithography

    Publication Year: 2002 , Page(s): 59 - 63
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB) |  | HTML iconHTML  

    In this paper we deal with the use of microstereolithography (μSL) to produce solid freeform objects from computer-assisted-design files. The μSL process is derived from stereolithography, and it is based on the photopolymerization through a dynamic mask generator of successive layers of photocurable resin, which permits us to produce accurate micro-objects with high aspect ratio and curved surfaces (due to the layer-by-layer nature of the process). This technology is extended to the manufacture of ceramic-polymer composite parts. To achieve this, we add dispersed alumina powder (at a volumic percentage of 24%) and a visible photoinitiator to a low viscosity diacrylate resin. The objects we made present interesting properties for microrobotic or microfluidic applications View full abstract»

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  • Optimal design for a ball grid array wire bonding process using a neuro-genetic approach

    Publication Year: 2002 , Page(s): 13 - 18
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This study presents an integrated method in which neural networks, genetic algorithms, and exponential desirability functions are used to optimize the ball grid array (BGA) wire bonding process. As widely anticipated, the BGA package will become the fastest-growing semiconductor package and push integrated circuit (IC) packaging to higher level of compactness and density. However, wire bonding in BGA is difficult owing to its high input/output (I/O) count, fine pitch wire bonds, and long wire lengths. This study addresses two fundamental issues in the semiconductor assembly facility on its quest toward a defect-free manufacturing environment. First, the problem of exploring the nonlinear multivariate relationship between parameters and responses and second, obtaining the optimum operation parameters with respect to each response in which the process should operate. The implementation for the proposed method was carried out in an IC assembly factory in Taiwan; results in this study demonstrate the practicability of the proposed approach View full abstract»

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  • Photolithographic packaging with selectively occupied repeated transfer (PL-Pack with SORT) for scalable film optical link multichip-module (S-FOLM)

    Publication Year: 2002 , Page(s): 19 - 25
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (325 KB) |  | HTML iconHTML  

    "Photolithographic packaging (PL-pack) with selectively occupied repeated transfer (SORT)" is proposed for optoelectronic microsystem integration. PL-pack with SORT integrates different types of thin-film device pieces into one substrate with desired configurations using an all-photolithographic process. A process design example is presented for a scalable film optical link multichip-module (S-FOLM). A preliminary estimation reveals that PL-Pack with SORT will achieve III-V epitaxial material saving of <1/100 and module cost reduction of <1/10, compared with flip-chip-bonding-based packaging. The result indicates that the process will save on cost and resources simultaneously. A critical issue is how to simplify the procedure for distributing thin-film device pieces onto a substrate. SORT is found to reduce the distribution step count typically by factor of <1/10-1/10000 compared with the conventional one-by-one method. PL-pack with SORT will be extended to the 3R process (reduce, reuse, recycle), which is generally applied to a variety of device/module fabrications View full abstract»

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  • Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

    Publication Year: 2002 , Page(s): 51 - 58
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies View full abstract»

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  • The effect of prebonding heat treatment on the separability of Au wire from Ag-plated Cu alloy substrate

    Publication Year: 2002 , Page(s): 5 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    The wire bonding technology that relies on subsequent wire separation of a connection has a possibility of becoming a key packaging technology in the environmentally friendly aspects of the recycling of mounting materials, such as the reworking of chip on board (COB) mounting and the application of the inter-poserless chip size package (CSP) in the manufacturing process. This study investigated how heat treatment before bonding affects separability at the ball bonding area. For the investigation, we used bonding pairs of Ag-plated Cu alloy substrate and An wire. Heating a board to 150°C before wire bonding degraded wire bondability but improved separability. An analysis of Ag plating by Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS) revealed that the heat treatment caused the Cu on the board to diffuse into the Ag plating and to deposit concentrations of Cu in the form of Cu(OH)2 and CuCl2 on the Ag surface View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University