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Electron Devices, IEEE Transactions on

Issue 5 • Date May 2002

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Displaying Results 1 - 25 of 38
  • Changes in the Editorial Board

    Page(s): 709
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    Freely Available from IEEE
  • The correlation resistance for low-frequency noise compact modeling of Si/SiGe HBTs

    Page(s): 863 - 870
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    The measurement of the correlation between the noise generators is a mandatory issue for the low-frequency noise modeling of bipolar transistors, and it is recognized as a very hard experimental task. In the present work, we introduce the concept of correlation resistance and we demonstrate that it can be usefully employed as a guideline for the low-frequency noise modeling in terms of intrinsic noise sources. As a proof of concept, the investigation technique is applied to submicron, BiCMOS-compatible Si/SiGe heterojunction bipolar transistors. It is pointed out that a satisfactory description of the transistor low-frequency noise behavior can be obtained by taking into account noise sources associated with surface recombination/fluctuation in the extrinsic base region View full abstract»

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  • Linearity and low-noise performance of SOI MOSFETs for RF applications

    Page(s): 881 - 888
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    The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands View full abstract»

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  • Quantum C-V modeling in depletion and inversion: accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs

    Page(s): 889 - 894
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    Presented in this paper is a quantum capacitance-voltage (C-V) modeling in depletion and inversion, incorporating the gate-depletion effect. The model enables fast and accurate extraction of the electrical thickness of gate oxide in deep submicron MOSFETs. The main quantum effect consists of the inversion capacitance of two-dimensional (2-D) electrons masking the true gate-oxide thickness, tOX. The quantum mechanical and gate depletion effects necessitate 6-10 Å equivalent oxide thickness correction, which is important for a tOX of 4 nm or less. The classical C-V analysis is compared with the quantum results in the light of the data, highlighting the difference between the models. The model is shown in good agreement with experiments and also with numerically calculated results View full abstract»

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  • A new mixed-mode sustain method to improve the luminous efficiency of alternating current plasma display panels

    Page(s): 762 - 769
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    In this paper, a new mixed-mode sustain method to improve the luminous efficiency of alternating current plasma display panels is proposed. An opposite discharge is initiated between successive surface sustain discharges during the sustain period. The opposite discharge not only has a higher ultraviolet photon collection factor, but also improves the surface sustain discharge efficiency for the production of ultraviolet photons. The experimental results show that a 21~59% improvement in luminous efficiency within a sustain voltage range of 170 V to 190 V is achieved by the new mixed-mode sustain driving approach, as compared with the conventional surface-type sustain method View full abstract»

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  • Damage generation and location in n- and p-MOSFETs biased in the Substrate-Enhanced Gate Current regime

    Page(s): 787 - 794
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    This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n+-poly n-MOSFETs and p+-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel View full abstract»

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  • Optimum design for a thermally stable multifinger power transistor

    Page(s): 902 - 908
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    The thermal stability of multifinger bipolar transistors has been analyzed theoretically. Coupled equations are solved to study the onset of instability and its dependence on the distributions of ballasting resistors. Analytical expressions were derived for the emitter ballasting distribution for optimum stable operation. Compared to conventional methods with uniform ballasting, the optimized design can significantly increase the stable operating current of the transistor. An absolutely stable operating condition is also derived. At this condition, the device never becomes unstable View full abstract»

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  • 4H-SiC rectifiers with dual metal planar Schottky contacts

    Page(s): 947 - 949
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    4H-SiC rectifiers with dual metal planar (DMP) Schottky contacts have been fabricated with a main titanium and an annular nickel contact. Fabricated diodes display low reverse leakage currents and low forward barrier heights. The diodes exhibited a high on/off current ratio (at 1 V/-500 V) exceeding 5.108 View full abstract»

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  • Modeling of the reverse characteristics of a-Si:H TFTs

    Page(s): 812 - 819
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    This paper investigates the reverse current-voltage (I-V) characteristics of inverted staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). Three mechanisms have been identified as the source of the reverse current: ohmic conduction, front channel conduction, and backchannel conduction. Ohmic conduction constitutes the physical limit for the reverse current and is due to the intrinsic conductivity of the a-Si:H and associated dielectric layers, which correlates with process integrity. The accumulation of holes and electrons at the front and back a-Si:H/a-SiNx:H interfaces, respectively, forms the basis of the other two leakage mechanisms. The relative dominance of the one or the other mechanism depends on bias conditions, TFT geometry, and process conditions. This paper identifies these sources of leakage current and examines the effect of the critical geometrical parameters (such as channel length and overlap length) and bias conditions on these leakage components. Physical models to predict bias and geometry dependences are presented for a quantitative analysis of the leakage current. Modeling results corroborate experimental observations of leakage current extracted from a large number of TFTs that are put in parallel for improved measurement accuracy. The physical parameters of the model provide a method for estimation of the significant interface and bulk properties of the structure View full abstract»

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  • Design methodology of the high performance large-grain polysilicon MOSFET

    Page(s): 795 - 801
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    A methodology to design high-performance MOSFETs on the large-grain polysilicon-on-insulator (LPSOI) film is presented. Due to the metal-induced lateral crystallization (MILC) process in the formation of LPSOI films, the polysilicon grain locations and orientations can be reasonably controlled. Therefore, the performance of an LPSOI MOSFET can be optimized by carefully selecting the orientation and grain location according to the size of the desired transistor. The effects of various design parameters including the distance from the nickel strip, relative source/drain position, transistor orientation, and layout geometry are investigated. A ladder layout method is proposed to provide scalability in the design of high performance LPSOI MOSFETs. A design guideline for designing LPSOI NMOSFETs with different dimensions is given View full abstract»

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  • Highly stable hydrogenated amorphous silicon germanium solar cells

    Page(s): 949 - 952
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    This article shows an optimized a-SiGe:H material that behaves highly stable in solar cells. The a-SiGe:H material is deposited by PECVD with high hydrogen dilution, near the microcrystalline deposition regime. We made various a-SiGe:H single solar cells to optimize the device design. The band gap in the central part of the cell is 1.53 eV. The hydrogen bonding configuration in the a-SiGe:H material suggests the presence of voids, however, the material has no noticeable sign of crystallinity. Light soaking experiments showed that the present single junction a-SiGe:H solar cells are highly stable. After one hour of light soaking, a slight improvement in fill factor is observed and an improvement in carrier collection in the red region is evident from spectral response. The stable a-SiGe:H material is incorporated as the bottom cell of a-Si:H/a-SiGe:H tandem solar cells. Unlike the single junction cell, this tandem cell slightly degrades under light soaking. This is solely the result of degradation of the a-Si:H top layer View full abstract»

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  • High-quality polycrystalline Si TFTs fabricated on stainless-steel foils by using sputtered Si films

    Page(s): 820 - 825
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    We have developed a low-temperature fabrication process (⩽ 200°C for high-quality polycrystalline Si thin-film transistors (poly-Si TFTs) on flexible stainless-steel foils. The fabrication processes is realized through sputter deposition of thin films, including active-Si and gate-SiO2 films, crystallization of Si films by KrF excimer laser irradiation, and inductively coupled plasma hydrogenation. High-quality n- and p-channel poly-Si TFTs are successfully fabricated without suffering from problems of substrate bending, film ablation, or cracking in films. The resulting n- and p-channel poly-Si TFTs showed mobilities of 106 and 122 cm2/V·s, respectively. This paper describes the deposition and properties of the sputtered Si films and the fabrication process and electrical characteristics of the poly-SiTFTs View full abstract»

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  • Comparison of DC and high-frequency performance of zinc-doped and carbon-doped InP/InGaAs HBTs grown by metalorganic chemical vapor deposition

    Page(s): 725 - 732
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    Zinc and carbon-doped InP/InGaAs heterojunction bipolar transistors (HBTs) with the same design were grown by metalorganic chemical vapor deposition (MOCVD). DC current gain values of 36 and 16 were measured for zinc and carbon-doped HBTs, respectively, and carrier lifetimes were measured by time-resolved photoluminescence to explain the difference. Transmission line model (TLM) analysis of carbon-doped base layers showed excellent sheet-resistance (828 Ω/□ for 600 A base), indicating successful growth of highly carbon-doped base (2×1019 cm-3). The reasons for larger contact resistance of carbon than zinc-doped base despite its low sheet resistance were analyzed. fT and fmax of 72 and 109 GHz were measured for zinc-doped HBTs, while 70-GHz fT and 102 GHz fmax were measured for carbon-doped devices. While the best performance was similar for the two HBTs, the associated biasing current densities were much different between zinc (4.0×10 4 A/cm2) and carbon-doped HBTs (2.0×105 A/cm2). The bias-dependant high-frequency performance of the HBTs was measured and analyzed to explain the discrepancy View full abstract»

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  • The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance

    Page(s): 826 - 831
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    The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (Kgate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum Kgate for different target subthreshold leakage currents has been identified View full abstract»

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  • Substrate and epitaxial issues for SiC power devices

    Page(s): 940 - 945
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    Realization of the full potential of semiconductor SiC for electronic and optical applications is critically dependent on the production of large diameter SiC single-crystals of high crystalline quality and controlled impurity content as well as high quality uniform epitaxial layers. In this paper, current substrate and epitaxial issues are presented in the light of recent results. Progress in monocrystalline SiC bulk crystal growth is characterized by the attainment of substrate diameters up to 100-mm; residual impurities in the 1015 cm-3 range; and micropipe densities as low as 1.1 cm-2 over an entire 50-mm diameter 4H-SiC wafer. Epitaxial growth progress is highlighted by growth rates as high as 50 μm/h, residual impurities of 1014 cm-3, and doping uniformities of less than 4.7% in commercial multiwafer reactors. Current materials challenges are the reduction of micropipes, dislocations and dislocation related defects View full abstract»

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  • Modeling of the CoolMOSTM transistor. II. DC model and parameter extraction

    Page(s): 923 - 929
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    An accurate dc model for the CoolMOSTM power transistor is presented. An elementary model consisting of an intrinsic MOSFET and a JFET to represent the drift region, is first discussed and it is pointed out that this is a rather poor model, needing improvements. Using device simulation results, it is shown that, by replacing the gate and drain voltages of the intrinsic MOSFET by appropriate "effective" voltages, a highly accurate model is obtained. A systematic procedure for parameter extraction is described and an implementation of the new model in the form of a SPICE subcircuit is given View full abstract»

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  • Evaluation of CVD/PVD multilayered seed for electrochemical deposition of Cu-damascene interconnects

    Page(s): 733 - 738
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    Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 μm minimum via size) resulting in a via resistance about 0.7 Ω. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 μm gate width. The propagation delay per inverter, which had an interconnect with 104 vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique View full abstract»

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  • A novel nonvolatile memory cell suitable for both flash and byte-writable applications

    Page(s): 802 - 807
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    The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors View full abstract»

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  • Modeling of the CoolMOSTM transistor - Part I: Device physics

    Page(s): 916 - 922
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    CoolMOSTM is a novel power MOSFET with a "superjunction" for its drift region, which results in a vastly improved relationship between the on resistance and breakdown voltage. The presence of the superjunction makes the device physics very interesting and complicated. In this paper, we present simulation results aimed at understanding the device operation both in the on state and in the off state. Quasi saturation of the drain current is analyzed, and it is shown that it can be prevented by increasing the doping density of the drift region. An analytic model of the JFET-like drift region is presented. A CoolMOSTM transistor model based on the simulation results described here will be presented in an accompanying paper View full abstract»

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  • Models for subthreshold and above-threshold currents in 0.1-μm pocket n-MOSFETs for low-voltage applications

    Page(s): 832 - 839
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    We present a model for subthreshold current in deep-submicrometer pocket n-MOSFETs based on the diffusion current transport equation, the quasi-two-dimensional (2-D) Poisson equation and a doping-density-dependent mobility model, and a model for above-threshold current in deep-submicrometer pocket n-MOSFETs based on the drift-diffusion current transport equation for nonuniformly doped MOSFETs, the charge-sheet approximation, a solution of the one-dimensional (1-D) Poisson equation, a quasi-2-D model for the velocity saturation region, longitudinal- and transverse-field-dependent mobility models. The analytic models for subthreshold and above-threshold currents are used to efficiently construct viable design spaces locating well-designed 0.1-μm pocket n-MOSFETs that meet all the device design specifications of off-state (leakage) current, on-state (drive) current, and power-supply voltage. The model for subthreshold current correctly predicts an increase in off-state current in sub-100 nm pocket n-MOSFETs. The model for above-threshold current generates ID-VDS characteristics of a variety of deep-submicrometer pocket n-MOSFETs View full abstract»

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  • Size dependence of the magnetic and electrical properties of the spin-valve transistor

    Page(s): 847 - 851
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    The electrical and magnetic properties of the spin-valve transistor (SVT) are investigated as a function of transistor size. A new fabrication process, designed to study the size dependence of the SVT properties, uses: silicon-on-insulator (SOI) wafers, a combination of ion beam and wet etching and a negative tone photoresist (SU8) as an insulating layer. The Si/Pt emitter and Si/Au collector Schottky barrier height do not depend on the transistor dimensions. The parasitic leakage current of the Si/Au collector is, however, proportional to its area. The relative collector current change with magnetic field is 240%, independent of size, while the transfer ratio starts to decrease for SVTs with an emitter area below 25 × 25 μm2. The maximum input current is found to be limited by the maximum current density allowed in the base (1.7 × 107 A/cm2), which is in agreement with the maximum current density for spin valves View full abstract»

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  • HCl-free selective epitaxial Si-Ge growth by LPCVD for high-frequency HBTs

    Page(s): 739 - 745
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    Low-temperature HCl-free selective silicon germanium epitaxial growth using low-pressure chemical vapor deposition was developed. By utilizing the incubation period of the poly-SiGe growth on SiO2 , sufficient selectivity was obtained without the use of HCl gas. The advantages of this HCl-free process are sufficient growth rate at low temperature (660°C) and capability of high-concentration boron doping without surface roughening. The thickness uniformity of the selectively grown layers throughout a wafer was good and the local loading effect did not appear. These results show the process can be used for fabricating heterojunction bipolar transistors (HBTs). The HBTs fabricated using the process have excellent yields and high-frequency characteristics, that is, 80-GHz cutoff frequency and 160-GHz maximum oscillation frequency. These characteristics and good uniformity of cutoff frequency throughout a wafer show that developed selective growth process can be applied to production of SiGe HBTs View full abstract»

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  • Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain

    Page(s): 718 - 724
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    In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate and bottom-gate is achieved by a noncritical chemical-mechanical polishing (CMP) step. A thin channel and a thick source/drain region self-aligned to the two gates are realized in the proposed process. Simulation results indicate that the self-aligned thick source/drain region leads to a significant reduction in the lateral electric field arisen from the applied drain voltage. N-channel poly-Si TFTs are fabricated with a maximum processing temperature of 600°C. Metal-induced unilateral crystallization (MIUC) is used to enhance the grain size of the poly-Si film. The fabricated SADG TFT exhibits symmetrical bi-directional transfer characteristics when the polarity of source/drain is reversed. The on-current under double-gate operation is more than two times the sum of that under individual top-gate and bottom-gate control. High immunity to short channel effects and kink-free current-voltage (I-V) characteristics are also observed in the SADG TFTs View full abstract»

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  • Analytical charge collection and MTF model for photodiode-based CMOS imagers

    Page(s): 754 - 761
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    An analytical charge collection model is derived to assess the impact of the photodiode size, doping profile and surface recombination velocity on the modulation transfer function (MTF) and the charge collection efficiency of CMOS imagers. The effects of the microlens and optical isolation are also quantitatively analyzed. The calculated MTF results agree well with measured data of fabricated imagers based on three different pixel designs View full abstract»

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  • A modified ramp waveform to reduce reset period in AC plasma display panel

    Page(s): 782 - 786
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    Recently, the voltage-controlled ramp (VCR) waveform has been used in the reset period prior to addressing for plasma display. In this method, if the ramp rise and fall times are significantly decreased in order to reduce the reset period, the dark room contrast ratio is decreased. To solve these problems, a modified current controlled ramp (CCR) waveform in the reset period is suggested. Experimental results for a 7-in model PDP show high contrast ratio without misfiring even for ramp rise/fall times of 20 μs. Moreover, the reset time can be reduced by about 30% compared with the VCR method under the same background luminance View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego