By Topic

IEE Proceedings - Computers and Digital Techniques

Issue 2 • Mar 2002

Filter Results

Displaying Results 1 - 4 of 4
  • Logic simulation methods for longest path delay estimation

    Publication Year: 2002, Page(s):53 - 59
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (767 KB)

    Two original methods are proposed for digital circuit delay estimation with logic simulation: direct circuit simulation (DCS) and inverse circuit simulation (ICS). With only one run of the logic simulator, the DCS method evaluates the longest path delay for each signal in the circuit for both rising and falling edges. If the delay to some primary output is too long to meet with the required circui... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional complexity estimation for large combinational circuits

    Publication Year: 2002, Page(s):39 - 45
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (676 KB)

    A disjoint cube-based method for the fast computation of M.G. Karpovsky's (1976, 1977) functional complexity measure is presented. A modification to the method for generating a disjoint sum-of-cubes representation for a combinational system is also presented, which results in improved speed performance in the generation of disjoint sums of cubes. The proposed algorithms are tested on several bench... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Incomplete reduction in modular arithmetic

    Publication Year: 2002, Page(s):46 - 52
    Cited by:  Papers (12)  |  Patents (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (705 KB)

    The authors describe a novel method for obtaining fast software implementations of the arithmetic operations in the finite field GF(p) with an arbitrary prime modulus p of arbitrary length. The most important feature of the method is that it avoids bit-level operations which are slow on microprocessors and performs word-level operations which are significantly faster. The proposed method has appli... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Branch prediction using both global and local branch history information

    Publication Year: 2002, Page(s):33 - 38
    Cited by:  Papers (3)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (594 KB)

    As the pipeline depth and issue rate of high-performance superscalar processors increase, the importance of an excellent branch predictor becomes more crucial to delivering the potential performance of a wide-issue, deep pipelined processor. Conventional two-level branch predictors predict the outcome of a branch either based on the local branch history information, comprising the previous outcome... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

Full Aims & Scope