Issue 4 • Date Dec. 2001
Author indexPage(s): 204 - 205| | PDF (178 KB)
Subject indexPage(s): 205 - 208| | PDF (184 KB)
Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devicesPage(s): 190 - 203
The gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD) robustness of CMOS devices are measured and compared in this paper. The operation principles of gate-grounded design, gate-driven design, and substrate-triggered design on CMOS devices for ESD protection are explained clearly by energy-band diagrams. The relations between ESD robustness and the devices with different triggered methods are also explained by transmission line pulsing (TLP) measured results and energy-band diagrams. The turn-on mechanisms of nMOS devices with triggered methods are further verified using the emission microscope (EMMI) photographs of the nMOS devices under current stress. The experimental results confirm that the substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices better than the gate-driven design. The human body model (HBM) ESD level of nMOS with a W/L of 400 μm/0.8 μm in a silicided CMOS process can be improved from the original 3.5 kV to over 8 kV by using the substrate-triggered design. The gate-driven design cannot continually improve the ESD level of the device in the same deep-submicron CMOS process View full abstract»
Effect of a thin ionized-metal-plasma deposited Cu layer on the properties and thermal stability of Cu-TaN-SiO2-Si structuresPage(s): 174 - 178
Cu-TaN-SiO2-Si structures, fabricated in a three-in-one system, were systematically investigated using various techniques. By depositing a thin plasma-metal-plasma (IMP) Cu layer on the TaN barrier prior to the copper film deposited using metal-organic chemical vapor deposition, the sheet resistance, uniformity, and adhesion of the metal in the Cu-TaN-SiO2-Si structures can be significantly improved. The thermal stability of the structures can also be enhanced due to the reduction of Cu diffusion and out-diffusion of Si, Ta, and O elements. These observations are of great value for application of chemical vapor deposition Cu-IMP Cu in multilevel interconnects of deep-submicron integrated circuits View full abstract»
This work presents experimental results concerning erratic behaviors in flash memories obtained by tracking the threshold voltage dynamics during any single erase operation and providing a deeper insight into their physical nature. The particular shape of the experimental erase curves allows the derivation of a nearly linear relationship between the amplitude of erratic threshold shifts and the equivalent barrier height controlling Fowler-Nordheim injection View full abstract»
The thermal resistance of InP-based single and double heterojunction bipolar transistors has been measured. The double heterojunction bipolar transistor (DHBT) device employs an InP collector to improve thermal conductivity and reduce the base-emitter junction temperature rise. DHBTs were grown with heavily doped InGaAs or InP sub-collectors for low resistance contacts. As expected, the all-InP collector (sub-collector and collector) had the lowest thermal resistance while the all-InGaAs collector (sub-collector and collector) had the highest thermal resistance. For a device with emitter size of 1 × 3 μm2, the room temperature thermal resistance of the all-InP collector DHBT was 3.9°C/mW. The DHBT with an InGaAs sub-collector had a thermal resistance of 5.6°C/mW, while the SHBT had a thermal resistance of 12.3°C/mW. Also compared were effects of device layout parameters on thermal resistance and the effect of the topside metal thickness. Devices with the largest perimeter-to-area ratio had the lowest thermal resistance when normalized to emitter area. HBTs with conservative alignment tolerances (L1) had similar thermal resistance to those with aggressive alignment tolerances (L2). The reduced parasitic capacitance of the L2-style SHBT improved the device f T from 150 to 183 GHz at 6.0-mA collector current. Alternately, the reduced parasitics allowed the SHBT to operate at 150 GHz fT at 2.9 mA, reducing the junction temperature rise by more than half. Doubling the topside metal thickness improved the thermal resistance by 31% at room temperature View full abstract»
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IEEE Transactions on Device and Materials Reliability is published quarterly. It provides leading edge information that is critical to the creation of reliable electronic devices and materials, and a focus for interdisciplinary communication in the state of the art of reliability of electronic devices, and the materials used in their manufacture. It focuses on the reliability of electronic, optical, and magnetic devices, and microsystems; the materials and processes used in the manufacture of these devices; and the interfaces and surfaces of these materials.
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Anthony S. Oates
Taiwan Semiconductor Mfg Co.