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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date April 2002

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Displaying Results 1 - 10 of 10
  • Correction to "Interconnect synthesis without wire tapering"

    Publication Year: 2002 , Page(s): 497
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (161 KB)  

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  • On automatic-verification pattern generation for SoC with port-order fault model

    Publication Year: 2002 , Page(s): 466 - 479
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB)  

    Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage View full abstract»

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  • A parallel built-in self-diagnostic method for embedded memory arrays

    Publication Year: 2002 , Page(s): 449 - 465
    Cited by:  Papers (12)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (475 KB)  

    In this paper, the authors propose a new built-in self-diagnosis method to simultaneously diagnose spatially distributed memory modules with different sizes. Based on the serial interfacing technique, the serial fault masking effect is observed and a bidirectional serial interfacing technique is proposed to deal with such an issue. By tolerating redundant read/write operations, they develop a new march algorithm called DiagRSMarch to achieve the goals of low test signal routing overhead, tolerable diagnostic time, and high diagnostic coverage. It can be proved that DiagRSMarch can identify all stuck-at, transition, state coupling, and dynamic coupling faults occurring in all memory arrays. Experimental results also demonstrate that the test efficiency of DiagRSMarch is highly dependent on memory topology, defect-type distribution, and degree of parallelism View full abstract»

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  • Architectural energy optimization by bus splitting

    Publication Year: 2002 , Page(s): 408 - 414
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (286 KB)  

    This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for minimum energy is formulated as a minimum-exchange bus split problem, which is shown to be NP-complete. The problem is solved heuristically by using a maximum-weight matching algorithm and combinatorial search. Experimental results show that the energy saving of split-bus architecture compared to monolithic-bus architecture varies from 16% to 50%, depending on the characteristics of the data transfer among the modules and the configuration of the split-bus. The proposed split-bus architecture can be extended to multiway split-bus architecture when large numbers of modules are to be connected View full abstract»

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  • A Monte Carlo approach for maximum power estimation based on extreme value theory

    Publication Year: 2002 , Page(s): 415 - 432
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (535 KB)  

    A Monte Carlo approach for maximum power estimation in CMOS very large scale integration (VLSI) circuits is proposed. The approach is based on the largely unexploited area of statistics known as extreme value theory. Within this framework, it attempts to appropriately model the extreme behavior of the probability distribution of the peak instantaneous power drawn from the power supply bus, in order to yield a close estimate of its maximum possible value. The approach features a relatively small number of necessary input patterns that does not depend on the circuit size, user-specified accuracy, and confidence levels for the final estimate, simplicity in the algorithmic implementation, noniterative single-loop execution, highly accurate simulation-based operation, and easy integration within the design flow of CMOS VLSI circuits. Experimental results establish the above claims and demonstrate the overall efficiency of the proposed approach to address the problem of maximum power estimation View full abstract»

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  • Circuit simplification for the symbolic analysis of analog integrated circuits

    Publication Year: 2002 , Page(s): 395 - 407
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB)  

    Presents a circuit simplification method for the symbolic analysis of a linear or linearized (small-signal) analog circuit. Its goal is to generate simplified signal flow graphs describing the circuit's behavior in well-defined frequency intervals. These frequency subranges are automatically constructed based on numerical calculation of the system's poles and zeroes. The circuit reduction has been implemented using graph manipulation techniques. The order in which these manipulations are applied is based on a tradeoff between the error and the level of simplification they introduce. The technique can be used to symbolically localize poles and zeroes and inspect their observability. This allows generating symbolic expressions for poles and zeroes, which in optimal conditions lead to simple, interpretable expressions. The technique can also be used as preprocessor to simplify a circuit before analyzing it with standard approximate symbolic analysis techniques. In that case, it helps overcoming the time and memory constraints related to those techniques. Experimental results show the effectiveness of the approach View full abstract»

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  • Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers

    Publication Year: 2002 , Page(s): 433 - 448
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (546 KB)  

    The authors present an accurate analytical method for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes use of the physically based MM9 MOSFET model (Velghe et al., 1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power law model. The resulting analytical model accounts for the effects of input slew time, device sizes, carrier velocity saturation effects, input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.18 and 0.35 μm technologies, showing significant improvements View full abstract»

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  • Min-cut partitioning with functional replication for technology-mapped circuits using minimum area overhead

    Publication Year: 2002 , Page(s): 491 - 497
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB)  

    Logic replication is known to be an effective technique to reduce the number of cut nets in partitioned circuits. A new replication model called functional replication is particularly useful for partitioning technology-mapped circuits. Functional replication differs from traditional replication because it considers the functional dependency of the different output signals of a logic cell on its input signals. Functional replication can lead to a higher reduction in the number of cut nets than traditional replication. In this paper, we give the first theoretical treatment of the min-cut partitioning problem with functional replication. We present a novel two-phase algorithm to compute a min-cut bipartition of a technology-mapped circuit with functional replication using a minimum amount of area overhead. Additionally, we show that our algorithm can be applied to improve the solution produced by any area-constrained functional replication partitioning heuristic View full abstract»

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  • Fault simulation and test algorithm generation for random access memories

    Publication Year: 2002 , Page(s): 480 - 490
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults View full abstract»

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  • A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters

    Publication Year: 2002 , Page(s): 377 - 394
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (866 KB)  

    With the shrinking of device sizes, random device variations become a key factor limiting the performances of high-resolution complementary metal-oxide-semiconductor (CMOS) current-steering digital-to-analog converters (DACs). In this paper, we present a novel design methodology based on statistical modeling of MOS transistor drain current that allows designers to explore different DAC architectures and to study the effects of technological variations on system performance without using time-consuming Monte Carlo simulations. This technique requires as a first step the estimation of the mean value and the autocorrelation function of a single stochastic process. This stochastic process models the device drain current and summarizes all the random sources associated with the process/device variations since the current represents the effect of all of them. Subsequently, on the basis of such an approach, a behavioral model of current-steering DACs has been developed. Finally, the statistical simulation of static performances such as differential nonlinearity and integral nonlinearity has been carried out for different DAC architectures based on the behavioral model previously derived View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu