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Electron Devices, IEEE Transactions on

Issue 4 • Date Apr 2002

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Displaying Results 1 - 25 of 26
  • Fast-switching and shallow saturation bipolar power transistors using corrugated base junctions

    Page(s): 673 - 678
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    A fast-switching and shallow saturation bipolar power transistor fabrication technology using corrugated base junctions, which does not require additional process steps, is proposed in this paper. Computer simulation shows that less excess minority and majority carriers stored in the base and the collector drift region cause the shallow saturation phenomena of the corrugated base transistors at the conduction stage, and that the corrugated base transistors have lateral built-in electric fields under the base electrode, which accelerate the movement of the minority carriers from the bulk to the surface and promote the recombination of excess electrons and holes in the base region. The turn-off times and the saturation voltages between the collector and the emitter are studied systematically as a function of the base masking oxide widths of the corrugated base region, which agree well with the simulation results View full abstract»

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  • Generalized image method with application to the thermal modeling of power devices and circuits

    Page(s): 679 - 686
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB)  

    A new analytical thermal model of multilayer substrates is presented. Based on a generalization of the method of images, the model is straightforward to implement and allows a clearer understanding of the effect of geometric and material parameters on the temperature field. Approximate expressions for the thermal resistance in multilayer substrates are derived for the first time. The generalized image method can be applied to solve similar problems which involve the solution of the Laplace equation in composite domains consisting of several layers. Typical examples are problems of the electrostatics and ohmic conduction phenomena View full abstract»

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  • Study of the color detection of a-Si:H by transient response in the visible range

    Page(s): 550 - 556
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    A new technique of color detection based on time-resolved charge collection during transient response measurement using a hydrogenated amorphous silicon detector has been proposed and experimentally demonstrated. The method based on the material intrinsic wavelength-filtering properties is implemented in color sensing by transient response of a detector to a combination of basic color light and voltage pulse. Resulting transient responses under different illumination and bias voltage conditions confirm considerable accuracy of proposed method. In particular, the best agreement of measured and calculated transient response curves has been obtained by using the spectral response of all three primary colors in calculations. It was observed that the presence of blue light drastically reduces the transient response to a chromatic light illumination. Finally, a voltage pulse influence to the basic colors transient response was found View full abstract»

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  • Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon

    Page(s): 687 - 692
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    Simultaneously fabricated RF power LDMOSFETs on thin-film SOI and bulk silicon wafers. This work compares their DC current-voltage (I-V), capacitance-voltage (C-V), S-parameter, and 1.9-GHz load-pull characteristics and explains differences between them. The SOI LDMOSFET performance is shown to be largely similar to the performance of an equivalent bulk silicon LDMOSFET, but there are important differences. The SOI LDMOSFET has moderately lower on-state breakdown voltage due to increased body resistance. It also has significantly improved power-added efficiency due to reduced parasitic pad losses View full abstract»

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  • Macroscopic simulation of quantum mechanical effects in 2-D MOS devices via the density gradient method

    Page(s): 619 - 626
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB)  

    Here, for the first time, are presented results of two-dimensional (2-D) simulations of metal-oxide-semiconductor (MOS) devices, including quantum mechanical modeling throughout the entire device region, calculated using the density gradient method. The importance of quantum mechanical modeling of the entire device structure, including the gate, source, drain, and channel, is demonstrated through one-dimensional (1-D) examples and through analysis of double and single-gated fully-depleted silicon-on-insulator (SOI) devices. A comparison of density gradient results with literature data is also presented View full abstract»

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  • Constant charge erasing scheme for flash memories

    Page(s): 613 - 618
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (275 KB) |  | HTML iconHTML  

    This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated View full abstract»

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  • Excellent cross-talk isolation, high-Q inductors, and reduced self-heating in a TFSOI technology for system-on-a-chip applications

    Page(s): 584 - 589
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    In this paper, novel structures are reported to improve the cross-talk isolation, the performance of on-chip inductors, and the self-heating in a thin-film silicon-on-insulator (TFSOI) technology. In these structures, p+ substrate contact rings are used to improve the cross-talk isolation, appropriately doped TFSOI layers are used for high-Q inductors, and source contacts connected to the substrate are used to minimize the self-heating problem. The p+ substrate contact rings provide -57 dB isolation (typically characterized for a device spacing of 100 μm) at 10 GHz, which is the best ever reported in TFSOI technology. A maximum Q-factor of 10.4 is obtained for TFSOI-layer shielded on-chip inductors. The inductor-to-inductor isolation is -62 dB (for a spacing of 100 μm) at 10 GHz, which is close to the ideal isolation of the open probes. The source contacts connected to the substrate improves the self-heating by 16%. The excellent cross-talk isolation performance, high-Q on-chip inductors, and reduced self-heating make the TFSOI technology a very suitable candidate for mixed signal system-on-a-chip (SOC) applications View full abstract»

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  • SiC power Schottky and PiN diodes

    Page(s): 665 - 672
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    The present state of SiC power Schottky and PiN diodes are presented in this paper. The design, fabrication, and characterization of a 130 A Schottky diode, 4.9 kV Schottky diode, and an 8.6 kV 4H-SiC PiN diode, which are considered to be significant milestones in the development of high power SiC diodes, are described in detail. Design guidelines and practical issues for the realization of high-power SiC Schottky and PiN diodes are also presented. Experimental results on edge termination techniques applied to newly developed, extremely thick (e.g., 85 and 100 μm) 4H-SiC epitaxial layers show promising results. Switching and high-temperature measurements prove that SiC power diodes offer extremely low loss alternatives to conventional technologies and show the promise of demonstrating efficient power circuits. At sufficiently high on-state current densities, the on-state voltage drop of Schottky and PiN diodes have been shown to be comparable to those offered by conventional technologies View full abstract»

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  • Effects of wave function penetration into the gate-oxide on self-consistent modeling of scaled MOSFETs

    Page(s): 693 - 695
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB)  

    Effects of wave function penetration into gate-oxide on properties of scaled nMOS devices in deep submicron regime are studied, taking into account the penetration effects on the solutions of both Schrodinger's and Poisson's equations. Numerical results show that penetration effects on properties of inversion layers become more important with scaling down of device dimensions. These effects are also more pronounced at strong inversion View full abstract»

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  • Hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon TFTs

    Page(s): 636 - 642
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    Hot-carrier injection is known to produce interface states and oxide trapped charge, which, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current flow. In this work, we analyze the hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon thin film transistors (TFTs) and a new model, which correlates the interface state generation with the hot carrier injection current, is proposed. The defect generation rate has been assumed to depend upon the product of hot electron and hole currents Jeh, and the resulting interface state distribution has been evaluated self-consistently with the current density and carrier concentration distributions. By successive iterations, a complete spatial and time evolution of the interface state distribution has been determined, and the electrical characteristics, calculated with these interface state distributions are in good agreement with the experimental data View full abstract»

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  • The design, characterization, and modeling of RF LDMOSFETs on silicon-on-insulator material

    Page(s): 643 - 651
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (934 KB)  

    This paper presents the first results of a practical 30 V RF LDMOSFET in silicon-on-insulator (SOI) material. Its complete electrical characteristics, DC and radio frequency (RF), are presented. Bulk silicon LDMOSFETs are popular in RF power applications, and SOI promises to improve device characteristics, enhance integration and provide high-temperature robustness. This work demonstrates that SOI LDMOSFETs can deliver performance comparable to bulk Si using an SOI CMOS foundry with only minimal process enhancements. To investigate the impact of feature sizing in the LDD and gate length on the static and RF performance, 12 devices were fabricated. Characterization was done at the wafer level and devices were packaged and used to construct a class A RF amplifier. The devices exhibited a subthreshold slope of 214 mV/decade, a transconductance of 30 mS, and fT up to 10.9 GHz. The amplifier had a maximum power output of 115 mW, gain of 14 dB, and a drain efficiency of 27% at Pout, max View full abstract»

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  • Effect of dead space on avalanche speed [APDs]

    Page(s): 544 - 549
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    The effects of dead space (the minimum distance travelled by a carrier before acquiring enough energy to impact ionize) on the current impulse response and bandwidth of an avalanche multiplication process are obtained from a numerical model that maintains a constant carrier velocity but allows for a random distribution of impact ionization path lengths. The results show that the main mechanism responsible for the increase in response time with dead space is the increase in the number of carrier groups, which qualitatively describes the length of multiplication chains. When the dead space is negligible, the bandwidth follows the behavior predicted by Emmons but decreases as dead space increases View full abstract»

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  • Technology and reliability constrained future copper interconnects. I. Resistance modeling

    Page(s): 590 - 597
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB)  

    A realistic assessment of future interconnect performance is addressed, specifically, by modeling copper (Cu) wire effective resistivity in the light of technological and reliability constraints. The scaling-induced rise in resistance in the future may be significantly exacerbated due to an increase in Cu resistivity itself, through both electron surface scattering and the diffusion barrier effect. The impact of these effects on resistivity is modeled under various technological conditions and constraints. These constraints include the interconnect operation temperature, the effect of copper-diffusion barrier thickness and its deposition technology, and the quality of the interconnect/barrier interface. Reliable effective resistivity trends are established at various tiers of interconnects, namely, at the local, semiglobal, and global levels. Detailed implications of the effect of resistivity trends on performance are addressed in the second part of this work View full abstract»

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  • Determination of deep ultrathin equivalent oxide thickness (EOT) from measuring flat-band C-V curve

    Page(s): 695 - 698
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (335 KB)  

    In this letter, a novel and simple method to determine deep ultrathin oxide thickness by measuring the MOS capacitance under the flat-band condition is reported. The mechanism of this method has been profoundly studied. The results determined by this method show good agreement with those using capacitance-voltage (C-V) simulation, ellipsometer, and high-resolution transmission electromicroscopy (HRTM) analysis for thin oxides (2~3 nm). The thickness of pure oxide extracted by this method in this experiment can be down to 1.4 nm despite the obvious C-V distortion View full abstract»

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  • Study of SILC and interface trap generation due to high field stressing and its operating temperature dependence in 2.2 nm gate dielectrics

    Page(s): 699 - 701
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    Reports study of metal-oxide-semiconductor (MOS) capacitors with 2.2 nm dry and N2O grown gate dielectrics. Interface trap generation during constant voltage stressing at different operating temperatures (from 22°C to 90°C) has been investigated. The effect of nitrogen annealing (20 min) at 400°C on high temperature stress-induced interface traps was also studied View full abstract»

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  • Floating-island TFT leakage caused by process step reduction

    Page(s): 576 - 583
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB)  

    The leakage mechanism for a top-gate thin-film transistor (TFT) produced using the fewest process steps in the industry is analyzed in order to achieve a high-contrast liquid crystal display (LCD). Using a T-shaped TFT structure, the OFF and ON channel lengths are defined independently, so that the leakage can be reduced with no ON current decrease View full abstract»

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  • On the transport equations in popular commercial device simulators

    Page(s): 702 - 703
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    The transport formulation used in many commercial semiconductor device simulators (for example DESSIS, ATLAS, and MEDICI) does not allow accurate modeling of electron-hole scattering in bipolar semiconductor devices such as diodes, bipolar junction transistors, and thyristors. This is especially important at low temperatures and/or high current densities View full abstract»

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  • Electroluminescent devices using a high-temperature stable GaN-based phosphor and thick-film dielectric layer

    Page(s): 557 - 563
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    Red, green, and blue light emission has been obtained from electroluminescent devices on glass using a high-temperature stable (HTS) GaN-based phosphor doped with rare earths (Eu, Er, Tm) and a screen-printed thick-film dielectric layer. The thick-dielectric electroluminescent (TDEL) structure consists of metal/dielectric/GaN/indium-tin-oxide/Corning 1737 glass. The BaTiO3-based ~20-40 μm thick-film dielectric layer has a dielectric constant of εr~500-1000 and breakdown voltage >300 V. Despite granularity of the dielectric layer, the emission is uniform to well-below pixel dimensions (<10 μm). Red GaN:Eu TDEL operated at 240 V and 1 kHz exhibits a luminance of 35-40 cd/m2. Under 140 lux illumination, the TDEL device structure exhibits a contrast ratio of 5:1 at 120 V, 1 kHz biasing, without the assistance of contrast-enhancement techniques. Accelerated aging tests of TDEL devices show 60 Hz operating lifetimes exceeding 1000 h at >95% brightness. The TDEL structure has advantages over current thin-film and thick-dielectric electroluminescent structures in flat panel display applications View full abstract»

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  • Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

    Page(s): 627 - 635
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (403 KB)  

    Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology View full abstract»

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  • Technology and reliability constrained future copper interconnects. II. Performance implications

    Page(s): 598 - 604
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB) |  | HTML iconHTML  

    For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity View full abstract»

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  • Status and prospects for SiC power MOSFETs

    Page(s): 658 - 664
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (545 KB)  

    SiC electronic device technology has made rapid progress during the past decade. In this paper, we review the evolution of SiC power MOSFETs between 1992 and the present, discuss the current status of device development, identify the critical fabrication issues, and assess the prospects for continued progress and eventual commercialization View full abstract»

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  • Simulation of quantum effects along the channel of ultrascaled Si-based MOSFETs

    Page(s): 652 - 657
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB)  

    Quantum transport simulations, including phase-breaking scattering, are used to observe the transition from classical to quantum transport in ultrascaled Si and SiGe heterostructure MOSFETs in order to gauge the potential effectiveness of semiclassical and pure phase-coherent quantum transport models as this transition is approached. It is shown that semiclassical models of transport along the length of the channel (as opposed to normal to the channel, where the importance of quantum mechanical effects has long been recognized) may remain reliable for channel lengths down to roughly 10 nm and perhaps beyond, and likely more reliable at this point than phase-coherent quantum transport simulations even when much of the transport is coherent/ballistic. As coherent transport effects within the channel eventually do become significant for ballistic carriers, the phase-breaking scattering rate, itself, also becomes a nonlocal function of the carrier's kinetic energy placing further demands on simulation. Simulations also reaffirm that for injection into the channel, the modeling of quantum transport effects such as tunneling, particularly in Si-SiGe heterostructure MOSFET's, will be important in much longer devices. However, even for this purpose it may not be possible to neglect the effects of inelastic scattering that can provide additional tunneling "paths." View full abstract»

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  • Inverse modeling of sub-100 nm MOSFETs using I-V and C-V

    Page(s): 568 - 575
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB) |  | HTML iconHTML  

    Direct quantitative two-dimensional (2D) profile characterization of state-of-the-art MOSFETs continues to be elusive. In this paper, we present a comprehensive indirect methodology that achieves that for sub-100 nm MOSFETs using combined current-voltage (I-V) and capacitance-voltage (C-V) data. An optimization loop minimizes the error between simulated and measured electrical characteristics by adjusting parameterized doping profiles. This technique possesses high sensitivity to critical 2D doping in the source/drain extensions and channel region as well as to structural details such as tox and physical gate length. Here we demonstrate the technique by characterizing two NMOS families (tox=3.3 nm and 1.5 nm with effective channel lengths down to 50 nm). We then follow up with an evaluation of the ability of inverse modeling to capture modern profiles using simulated devices and I-V data. We show that extracted profiles exhibit decreased root mean square error (RMSE) as the doping parameterization becomes increasingly comprehensive of doping features (i.e., implants or doping pile-up) View full abstract»

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  • An anomalous device degradation of SOI narrow width devices caused by STI edge influence

    Page(s): 605 - 612
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show a reduction in mobility (NMOSFETs and PMOSFETs) and an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel widths. The degradation of MOSFET yield in SOI MOSFETs with the STI is found to be dependent on the device width since the contribution of the interface roughness (or damage) between the STI and the channel formed during the dry etch process becomes significant with the decrease of channel width and the increase of channel length. From the charge-pumping results, the interface state (Nit) generated by the STI process was identified as the cause of the anomalous degradation View full abstract»

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  • Characterization of the novel polysilicon TFT with a subgate coupling structure

    Page(s): 564 - 567
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB)  

    Proposed and fabricated a novel polysilicon thin film transistor (poly-Si TFT) with a subgate coupling structure that behaves as an offset gated structure in the OFF state while acting as a conventional nonoffset structure in the ON state. The OFF state leakage current of the new TFT is two orders of magnitude lower than that of the conventional nonoffset TFT, while the ON current of the new TFT is one order of magnitude higher than that of the offset TFT and is almost identical to that of the conventional non-offset TFT. The ON/OFF current ratio of the new TFT is greatly improved by two orders of magnitude. No additional photo-masking steps are required to fabricate the subgate of the new TFT and its fabrication process is fully the same as the conventional nonoffset TFTs View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology