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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 12 • Date Dec. 2001

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Displaying Results 1 - 11 of 11
  • Author index

    Page(s): 1155 - 1159
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    Freely Available from IEEE
  • Subject index

    Page(s): 1160 - 1175
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    Freely Available from IEEE
  • Multimode mean field annealing technique to design recursive digital filters

    Page(s): 1151 - 1154
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    The multi-mode mean field annealing (MM-MFA) approach to combinatorial optimization is introduced as a tool to design recursive infinite-impulse response (IIR) digital filters with discrete coefficients. As an application example demonstrating the potential of the method we consider the design of structurally passive IIR digital filters realized as the sum of two all-pass functions. The new design technique facilitates the solution of nontrivial filter design problems such as satisfying a general frequency specification by solving a combinatorial optimization problem over discrete coefficients and a max-norm cost. The final solution is not guaranteed to be a globally optimal solution but the convergence time is short enough to allow interactive design even for large problems View full abstract»

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  • Supply noise insensitive PLL design through PWL behavioral modeling and simulation

    Page(s): 1137 - 1144
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    This brief presents a design flow for a supply noise insensitive (SNI) phase-locked loop (PLL). The influence on the PLL jitter of each noise component having high/low bandpass filter characteristics is investigated in the time domain. Acquisition time, tracking range, lock range and jitter are key parameters of a PLL system, and they are evaluated with piecewise linear (PWL) behavioral modeling. Finally, the SNI-PLL circuit having worst-case -45-dB power supply noise rejection based on the behavioral simulation results is implemented View full abstract»

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  • A digital signal processor with programmable correlator array architecture for third generation wireless communication system

    Page(s): 1110 - 1120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (449 KB) |  | HTML iconHTML  

    A digital signal processor (DSP) with programmable correlator array architecture is presented for third generation wireless communication system. The programmable correlator array can be reconfigured. as a chip match filter, code group detector, scrambling code detector, and RAKE receiver with low power consideration. The architecture and instruction set of the proposed DSP are specially designed for several key operations of wireless communications, such as channel estimation for RAKE combining, Viterbi algorithm and finite-impulse response filtering. The proposed DSP outperforms other previously presented communication digital signal processors in terms of several crucial operations of wireless applications. A chip of the proposed DSP was implemented using hybrid design method where the timing critical components were full-custom designed and the other parts were cell-based designed under TSMC 0.35-μm CMOS 1P4M technology. We believe that the proposed system architecture would be useful for upcoming 3G mobile terminal applications View full abstract»

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  • Two "noninvasive" techniques for syllabic companding in signal processors

    Page(s): 1085 - 1098
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    Two novel methods are described for syllabic companding in signal processors. These methods make state variable updating unnecessary, for piecewise constant input and output gains. Measurements and simulations are used as confirmation of the validity of the proposed techniques View full abstract»

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  • Low-power fully differential CMOS filter for video frequencies

    Page(s): 1144 - 1148
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    The authors describe a new low-power fully differential second-order continuous-time low-pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low-power consumption and large dynamic range. The ideal integrator is realized using an internally compensated op-amp consisting of only current mirrors and voltage buffers, while the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5-V power supply, cutoff frequency can be tuned from 3.5 to 8 MHz, dynamic range is better than 67 dB and power consumption is less than 1.7 mW View full abstract»

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  • Low-power design of direct conversion baseband DECT receiver

    Page(s): 1121 - 1131
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    Portable terminals supporting the Digital Enhanced Cordless Telecommunications (DECT) standard have entered the world market in the last few years. For such devices low energy dissipation is of critical importance. In this paper, the design of a low-power fully digital baseband receiver that embodies innovative and conventional low-power optimizations is presented. The proposed baseband receiver complies with the DECT standard as far as digital modem functions are concerned. The developed energy-conscious, low complexity DECT demodulation algorithm and the low-power hardware architecture are described in a detailed manner View full abstract»

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  • On optimal tapering of FET chains in high-speed CMOS circuits

    Page(s): 1099 - 1109
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    Transistor tapering is a technique applied to optimize the geometries of CMOS transistors in high-performance circuit design with a view to minimizing the delay of a FET network. Currently, in a long FET network where MOS devices are stacked over one another to form a series chain network, the dimensions of the transistors are decreased from the bottom transistor to the top transistor in a manner where the width of transistors is tapered linearly or exponentially. However, it has not been mathematically proved whether either of these tapering schemes yields optimal results in terms of minimization of switching delays of the network. We rigorously analyze MOS circuits consisting of long FET chains under the widely used Elmore delay model and derive the optimality of transistor tapering by employing variational calculus. We demonstrate that neither linear nor exponential tapering alone minimizes the discharge time of the FET chain. Instead, a composition of exponential and constant tapering actually optimizes the delay of the network. Both analytical and simulation results are always consistent View full abstract»

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  • CFOA based inverting amplifier bandwidth enhancement

    Page(s): 1148 - 1150
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    A theoretical study of the high frequency characteristic of an inverting amplifier based on a current feedback operational amplifier is presented. It is shown that the amplifier bandwidth and step response can be improved using a pole-zero compensation technique. Simulation and experimental results agree with the theory View full abstract»

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  • Adaptive recursive algorithm for complementary subspace-based blind multiuser detection

    Page(s): 1132 - 1136
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    A novel blind adaptive multiuser detection scheme, the linear decorrelating detector (LDD), based on a concept of the complementary subspace is proposed. Under this scheme, the information bits can be estimated from the received signal with the prior knowledge of the desired user's signature waveform and its timing. The technique has two key elements: a geometric notion of the LDD and the subspace-based concept to estimate the orthogonal complement of the interfering space. It is then shown that the LDD can be formulated in terms of the interference space constructed from the received signal, and the desired user's signature waveform. The interference space components can be adaptively estimated using the modified power-based methods with only O((K-1) N) flops of computation at each iteration, where N is the processing gain, and K is the number of active users in the channel. The novel blind adaptive detector offers lower computational complexity. The proposed blind multiuser detection offers the optimal near-far resistance, low computational complexity, and resistance against the orthogonality error of the estimated interference space View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope