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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Jan 2002

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Displaying Results 1 - 4 of 4
  • Code compression techniques using operand field remapping

    Publication Year: 2002, Page(s):25 - 31
    Cited by:  Papers (2)  |  Patents (11)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (952 KB)

    Dictionary-based code compression stores the most frequently used instruction sequences in a dictionary and replaces the occurrences of these sequences in the program with codewords. The large dictionary size is due mainly to many instruction sequences which are different only in their operands, but are otherwise the same. The operand factorisation technique divides the expression tree into a tree... View full abstract»

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  • Removing multiple redundancies in combinational circuits

    Publication Year: 2002, Page(s):1 - 8
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (861 KB)

    Redundancy removal is an important step in combinational logic optimisation. After a redundant wire is removed, other originally redundant wires may become irredundant, and some originally irredundant wires may become redundant. When multiple redundancies exist in a circuit, this creates a problem, where we need to decide which redundancy to remove first. The authors present both a theoretical ana... View full abstract»

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  • Design of efficient architectures for discrete orthogonal transforms using bit level systolic structures

    Publication Year: 2002, Page(s):17 - 24
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (757 KB)

    Discrete orthogonal transforms (DOTs) are important in many applications, including image and signal processing. Novel 1D and 2D bit-level systolic architectures are presented for the efficient implementation of DOTs for image and signal processing. The authors describe the design methodology of the techniques based on the Baugh-Wooley (1973) algorithm, and the associated design, including a case ... View full abstract»

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  • E-BIST: enhanced test-per-clock BIST architecture

    Publication Year: 2002, Page(s):9 - 15
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (571 KB)

    A new enhanced built-in self-test (E-BIST) architecture, that is suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS (Self-Test Using MISR and Parallel Shift-register sequence generators), which uses a linear feedback shift register (LFSR) as the test generator, a multiple-input shift register (MISR) as the response compactor and shift register latch (SRL)... View full abstract»

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Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

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