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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2002

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Displaying Results 1 - 15 of 15
  • Editorial

    Page(s): 1
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    Freely Available from IEEE
  • Data mining for improving a cleaning process in the semiconductor industry

    Page(s): 91 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (227 KB) |  | HTML iconHTML  

    As device geometry continues to shrink, micro-contaminants have an increasingly negative impact on yield. By diminishing the contamination problem, semiconductor manufacturers will significantly improve wafer yield. This paper presents a comprehensive and successful application of data mining methodologies to the refinement of a new dry cleaning technology that utilizes a laser beam for the removal of micro-contaminants. Experiments with three classification-based data mining methods (decision tree induction, neural networks, and composite classifiers) have been conducted. The composite classifier architecture has been shown to yield higher accuracy than the accuracy of each individual classifier on its own. The paper suggests that data mining methodologies may be particularly useful when data is scarce, and the various physical and chemical parameters that affect the process exhibit highly complex interactions. Another implication is that on-line monitoring of the cleaning process using data mining may be highly effective View full abstract»

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  • Characterization and modeling of on-chip spiral inductors for Si RFICs

    Page(s): 19 - 29
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    The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance. View full abstract»

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  • Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

    Page(s): 9 - 18
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    In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield View full abstract»

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  • Improvement in ultrathin rapid thermal oxide uniformity by the control of gas flow

    Page(s): 102 - 107
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB) |  | HTML iconHTML  

    A methodology to improve the temperature uniformity for the wafer in a rapid thermal processing (RTP) system is presented. The work aims at the temperature compensation at the wafer surface by thermal convection. From simulation results of the flow field, it is seen that the cold gas, while flowing from the periphery of the wafer toward the wafer center, causes a lower pressure at and around the center. This lower pressure is due to the flow away of gas by buoyancy and it aggregates thermal nonuniformity. A technique is suggested that consists of suppressing the upward gas flow using a transparent quartz cap above the monitored wafer. Simulation and experimental results show that by implementing this technique, the temperature uniformity of the wafer is improved View full abstract»

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  • A statistical analysis of copper bottom coverage of high-aspect-ratio features using ionized physical vapor deposition

    Page(s): 30 - 38
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    Ionized physical vapor deposition (IPVD) is a new method for depositing metal into high-aspect-ratio features used as interconnects in microelectronic fabrication. It is similar to sputtering except that a portion of the metal flux to the substrate is ionized. We show how a high ionized-metal-flux fraction (IMFF) at the deposition location improves the bottom coverage of deposited metal films. To measure IMFF, a tool was developed, that biased the front surface of a microbalance crystal directly so as to repel ions. Cu IMFFs to the substrate of greater than 90 % along with deposition rates of 1000 Å/min can be achieved. A statistical model for both IMFF and total metal flux as a function of four control variables, chamber height, Ar pressure, ionizer power, and sputter power, was developed View full abstract»

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  • Real-time predictive control of photoresist film thickness uniformity

    Page(s): 51 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB) |  | HTML iconHTML  

    With the trends toward larger wafer size and the linewidth going below 100 nm, one of the challenges is to control the resist thickness and uniformity to a tight tolerance in order to minimize the thin-film interference effect on the critical dimension. In this paper, we propose a new approach to improve resist thickness control and uniformity through the softbake process. Using an array of thickness sensors, a multizone bakeplate, and advanced control strategy, the temperature distribution of the bakeplate is manipulated in real time to reduce resist thickness nonuniformity. The bake temperature is also constrained to prevent the decomposition of a photoactive compound in the resist. We have experimentally obtained a repeatable improvement in resist thickness uniformity from wafer-to-wafer and across individual wafers. Thickness nonuniformity of less than 10 Å has been obtained. On average, there is 10 × improvement in the thickness uniformity as compared to conventional softbake process View full abstract»

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  • A novel one step integration of edge-emitting laser diode with micro-elliptical lens using focused ion beam direct deposition

    Page(s): 2 - 8
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    An edge-emitting laser diode (LD) integrated with a microlens on its emitting surface for the purpose of collimating and fiber coupling is introduced in detail in this paper. A micro-elliptical lens is adopted for the integration in terms of divergence angle in both parallel and transverse directions. The lens with dimensions of 50 μm×30 μm×4 μm is microfabricated on the emitting surface of the laser diode with operating wavelength of 635 nm directly by focused ion beam (FIB) deposition function. The SiO2 deposition is realized by programming of the FIB machine. It is shown by test results that the focused spot size in the parallel and transverse propagation directions are 7.9 and 9.1 μm (at site of 1/e2), respectively, and the coupling efficiency of the compact and miniaturized system can reach as high as 71%. Measured far-field angles (full angle) with the microlens in both parallel and transverse directions are 2.2° and 1.2°, respectively. Compared with the original divergence angles of 31° and 14° without the micro-elliptical lens, they were greatly reduced by this method View full abstract»

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  • A wavelet-based procedure for process fault detection

    Page(s): 79 - 90
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    To detect faults in a time-dependent process, we apply a discrete wavelet transform (DWT) to several independently replicated data sets generated by that process. The DWT can capture irregular data patterns such as sharp "jumps" better than the Fourier transform and standard statistical procedures without adding much computational complexity. Our wavelet coefficient selection method effectively balances model parsimony against data reconstruction error. The few selected wavelet coefficients serve as the "reduced-size" data set to facilitate an efficient decision-making method in situations with potentially large-volume data sets. We develop a general procedure to detect process faults based on differences between the reduced-size data sets obtained from the nominal (in-control) process and from a new instance of the target process that must be tested for an out-of-control condition. The distribution of the test statistic is constructed first using normal distribution theory and then with a new resampling procedure called "reversed jackknifing" that does not require any restrictive distributional assumptions. A Monte Carlo study demonstrates the effectiveness of these procedures. Our methods successfully detect process faults for quadrupole mass spectrometry samples collected from a rapid thermal chemical vapor deposition process View full abstract»

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  • Solution of pattern matching inspection problem for grainy metal layers

    Page(s): 118 - 126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    In this paper, we demonstrate a new method of improving the defect controllability of grainy metal layers, for example, Hot-Al-Cu wiring, by enhancing the practical sensitivity of in-line inspectors. The problem in increasing practical sensitivity is the nuisance counts caused by grain boundaries, which do not cause electrical failures. We propose a method of decreasing the signal from the grain boundaries. On the grayscale images taken by pattern matching inspectors, grain boundaries are observed as gray on Hot-Al-Cu wiring, which is observed as white. If the illumination brightness is increased, the gray level of the grain boundaries becomes higher and saturates at the upper limit of grayscale, i.e., white. On the other hand, the gray level of the wiring stays white. Thus the signal, the grayscale difference between the grain boundaires and the wiring, can be decreased to almost zero. We call this phenomenon the "saturation effect." Our experimental results prove that the saturation effect due to illumination brightness optimization successfully cancels the nuisance counts caused by grain boundaries. The practical sensitivity limit is enhanced from 0.8 to 0.4 μm. This solution will greatly improve the defect controllability of grainy metal layers View full abstract»

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  • Hydrodynamic characteristics of the thin fluid film in chemical-mechanical polishing

    Page(s): 39 - 44
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    Presents results of an analytical study involving the kinematics and pressure distribution developed in the wafer-pad interface during a chemical-mechanical polishing (CMP) process. The mathematical modeling of the kinematics and dynamics of the interface is simplified by the use of the circumferential average technique yielding equations that are readily solved. The analytical results are in reasonably good agreement with those reported by previous authors using the direct numerical simulation of the Navier-Stokes equations. Furthermore, the present analysis clearly demonstrates the physical significance in the CMP process contributed by a variety of the operating parameters including rotation speed, offset of rotational axis, wafer curvature, slurry viscosity, and thickness of fluid film between the wafer and pad View full abstract»

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  • High-throughput mapping of short-range spatial variations using active electrical metrology

    Page(s): 108 - 117
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    Spatial variations of parameters in semiconductor manufacturing, such as critical dimension (CD) and overlay, have significant impact on the performance and yield of integrated circuits (IC). Among these spatial variations, the variations of parameters between transistors separated by a very short spatial distance such as 1 μm to 100 μm (intertransistor variations) can be particularly hazardous for those types of ICs that require exact transistor-transistor matching. To measure these intertransistor variations, both high-throughput and high-spatial-sampling-density beyond the scope of currently available metrology tools are needed. We have thus developed an active electrical metrology method of measuring intertransistor variations using on-chip, active, electrically addressable arrays of test structures to provide the high-throughput (5 μs/data point) and high-density (3 μm/grid spacing) needed. Test chips were designed and fabricated on a HP 0.35-μm process, and the testing configuration was set up to optimize throughput and precision. This method was verified with the measurements of on-chip calibration arrays. The spatial variations of both intertransistor CD (effective gate length) and overlay (between poly/diffusion) within the test chips were mapped with this method. For these circuits, the intertransistor CD variations were found to depend primarily on the layout, whereas the intertransistor overlay variations were found to be dominated by errors of the pattern generator used to fabricate the masks View full abstract»

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  • Visualized characterization of slurry film between wafer and pad during chemical mechanical planarization

    Page(s): 45 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    Chemical mechanical planarization (CMP) has emerged recently as an indispensable processing technique for planarization in submicrometer multilevel very large scale integration (VLSI). The demand from industry for fast material removal and a high degree of uniformity has been a serious challenge for the advancement of this key technology. Among various process aspects, the slurry flow between wafer and pad plays an important role in the pursuit of these goals. This study provides a visualized characterization of the amount and distribution of the fluid film between the wafer and pad. The fluid film is analyzed by the digital picture obtained through the transparent carrier and dyed fluid. The effects of process parameters are extensively investigated, including platen and carrier speed, pad design, rinsing location, and flow rate of slurry and wafer size. Suggestions for process recipes aiming at fast and uniform CMP are drawn based on the current results View full abstract»

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  • Artificial neural-network-based diagnosis of CVD barrel reactor

    Page(s): 71 - 78
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    This paper presents an artificial neural network (ANN) based diagnostic strategy applied to a chemical vapor deposition (CVD) barrel reactor of the type commonly used in silicon epitaxy. The strategy is based on the spatial variation of the rate of deposition of silicon on a facet of the reactor. Our hypothesis is that this spatial variation, quantified as a vector of variously measured standard deviations, encodes a pattern reflecting the state of the reactor. Therefore, a process fault (event) can be diagnosed by decoding the pattern by an ANN. We implemented this simple scheme by simulating different events by means of a regression model relating the rate of deposition to the process settings. Three different events were simulated and various ANNs were trained to detect and classify these events. It is shown that a single ANN or a combination of ANNs does an excellent job. We also demonstrate that the threshold rule for setting the threshold of a binary output neuron performing a classification task enhances the diagnostic performance. A novel multiple expert scheme that refers to several ANNs trained in the same classification task for decision-making in order to resolve ambiguities and improve the reliability of the final decision is presented and shown to be effective View full abstract»

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  • MBPCA application for fault detection in NMOS fabrication

    Page(s): 60 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    This paper describes the application of model-based principal component analysis (MBPCA) to the identification and isolation of faults in NMOS manufacture. In MBPCA, multivariate statistics are applied to the analysis of the portion of the data variance that is unexplained by models based on material and energy balances carried out on the unit operations used in manufacture. It is demonstrated that the failure detection and isolation performance achievable using the model-based procedure exceeds that of commonly used univariate SPC or conventional PCA approaches View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721