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Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov. 2001

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Displaying Results 1 - 25 of 30
  • Foreword contributions from the 50th electronic components and technology conference

    Page(s): 418
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  • Foreword

    Page(s): 463
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    Freely Available from IEEE
  • Microfixtured assembly for lensed optoelectronic receivers

    Page(s): 586 - 589
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    A new approach for passively aligning, fixing and lens-coupling a photodetector array to an array of optical fibers is described. A two-part assembly is constructed from two pieces of silicon that have different crystallographic cuts. One piece, the base, is fabricated from (100) silicon and contains features for positioning the photodetector chip, the optical fibers and a mating second piece. That second piece, the lens insert, is fabricated from (110) silicon and contains the lenses plus features for mating with the first piece and establishing the input/output focal distances View full abstract»

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  • Author index

    Page(s): 604 - 608
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    Freely Available from IEEE
  • Subject index

    Page(s): 608 - 619
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    Freely Available from IEEE
  • Electrical characterization of a 500 MHz frequency EBGA package

    Page(s): 534 - 541
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    We developed a high-speed enhanced ball grid array (EBGA) package that can accommodate a 500 MHz ASIC with 15 W of power consumption. This package uses 32 pairs of low voltage differential signals with 400 mV full amplitude and 240 ps risetime as its highest signal speed. The differential signal pairs are designed to run all along with an isometric length including bonding wire, trace, via, and ball in order to cancel out the common mode noise. Adjacent two differential signal pairs are grouped into a channel, which is also designed to have an isometric length. This channel forms a set of parallel transmission paths. The transmission line was formed with characteristic impedance of 60 Ω within a substrate in terms of strip line configuration. This package has a nonstub configuration using electroless nickel and gold plating. The ground pad is connected to the ground plane through the sidewall of the cavity, which is the nearest path in order to reduce ground inductance-per-pin down to 12-24 pH. Time domain waveform was simulated at the frequency of 500 MHz as the electrical characteristics of this package. The time domain waveform in an actual package was measured at risetime of 120 and 240 ps, which corresponds to 500 and 800 MHz of frequency, respectively. The simulated waveform correlates very well with the measured waveform. Signal integrity was excellent, which had small overshoot-undershoot and crosstalk noise less than 10%. Differential skew and channel skew were minimized to less than 10 ps to achieve a parallel transmission. We confirmed this at system level using our package with a 500 MHz ASIC. With our package we are able to accommodate an 800 MHz ASIC based on the time domain waveform results View full abstract»

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  • Interconnections based on Bi-coated SnAg solder balls

    Page(s): 515 - 520
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    To decrease the bonding temperature required for eutectic SnAg solder, SnAg solder bumps were chemically coated with a pure Bi layer. During heating, a low melting eutectic forms between the Bi coating and the SnAg, enabling bonding at temperatures below the melting points of either pure Bi or SnAg solder. As the composition of the molten solder changes toward more dilute Bi concentrations, the melting point in the joint region increases and the joint solidifies. After solidification the joints will no longer melt at the original bonding temperature. Bi-coated SnAg solder balls were joined to metallized substrates at temperatures ranging from 180°C to 250°C. The microstructure at the joint interface was characterized by the SEM/EDS technique. As expected, at 180°C the Bi-coated SnAg solder balls melted only locally at the interfacial regions between the ball and the substrate and so retained their spherical shape during bonding. After solidification there were a lot of small Bi precipitates in the joint region. At higher temperatures, the wetting was evidently better, and there were less Bi precipitates, because the melt was more dilute in bismuth. In all cases, Bi formed relatively small, equi-axed precipitates instead of the eutectic structure found in eutectic Sn-Bi solder joints View full abstract»

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  • Advances in multichannel MultiGbytes/s bit-parallel WDM single fiber link

    Page(s): 456 - 462
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    For ultra-high-speed single media parallel interconnects, an all optical single fiber WDM format of transmitting parallel bits rather than a fiber ribbon format-where parallel bits are sent through corresponding parallel fibers in a ribbon format, can be the media of choice. Here, we discuss the realization of a multi-km×Gb/s bit-parallel WDM (BP-WDM) single fiber link. The distance-speed product of this single fiber link is more than several orders of magnitude higher than that of a fiber ribbon link. The design of a 12 b parallel channels WDM system operating at 1 Gb/s per channel rate through a single fiber is first presented. Experimental results for a two channel system operating at that rate are given. Further improvement of distance-speed product for the BP-WDM link can be obtained with JPL's newly developed 20 Gb/s per channel laser diode array transmitter. Also, new computer simulation results on how a large amplitude co-propagating pulse may induce pulse compression on all the co-propagating data pulses, thereby improving the shaping of these pulses for a WDM system, are presented and discussed. The existence of WDM solitons is also shown View full abstract»

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  • High performance package designs for a 1 GHz microprocessor

    Page(s): 470 - 476
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    This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case View full abstract»

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  • Reaction of solder with Ni/Au metallization for electronic packages during reflow soldering

    Page(s): 493 - 498
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    Gold over Ni is one of the most common surface finishes for Cu soldering pads in ball-grid-array (BGA) and other electronic packages. The Au layer is for oxidation protection, and the Ni layer serves as a solderable diffusion barrier. In this study, eutectic Pb-Sn solder-balls were reflowed on the Au/Ni/Cu pads, and the chemical interactions between the solder and the surface finish were studied. Quenched-in microstructures at different stages of the reflow were carefully examined using the scanning electron microscopy. It was found that the solder melted locally along the solder/pad interface at the very early stages of the reflow before the whole solder ball had reached the Pb-Sn eutectic temperature. This was because a ternary eutectic reaction L=(Pb)+(Sn)+AuSn4 occurred at 177°C, six degrees below the Pb-Sn eutectic temperature. Four distinct stages were identified for the reflow process. The four stages are: (1) partial melting of solder balls and the initial reaction of Au with Sn; (2) complete reaction of An with Sn; (3) separation of (AuxNi1-x)Sn4 from the pad; (4) complete melting of solder balls and the reaction of Ni with Sn. After a typical reflow, with a 225°C peak reflow temperature and 115 s reflow time, all the An and Au-bearing intermetallic compounds left the interface and the only intermetallic compound at the interface was Ni3Sn4 with a thickness of about 2 μm View full abstract»

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  • Multiple-chip precise self-aligned assembly for hybrid integrated optical modules using Au-Sn solder bumps

    Page(s): 569 - 575
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    We have developed a novel three-dimensional high precision self-aligned assembly using stripe-type Au-Sn solder bumps and a micro-press solder bump formation method. This produces a high bonding precision of 1 μm for optical device assembly in both lateral and vertical directions without the need for time-consuming optical axes alignment. Furthermore, we tested a hybrid integrated 4×4 optical matrix switch, in which multiple SSC-SOAG arrays were simultaneously positioned and optical fibers were passively positioned on a silica based PLC platform using this technology. Four optical chips and seven wiring chips are assembled on a planar lightwave circuit (PLC) platform. The insertion loss for each of these paths at an injection current of 40 mA was within a range of 9±4 dB. The average extinction ratio was 40 dB. This self-aligned assembly technology was shown to be useful for building hybrid-integrated multichannel optical network components View full abstract»

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  • A hybrid 2-D ADI-FDTD subgridding scheme for modeling on-chip interconnects

    Page(s): 528 - 533
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    This paper presents a novel technique for extracting the propagation characteristics of on-chip interconnects. A hybrid two-dimensional subgridding scheme, based on a combination of the finite-difference time-domain (FDTD) method and the alternating-direction implicit (ADI-)FDTD technique, is utilized. The ADI-FDTD scheme is used for fine grid in the vicinity of the metallic etch, while the coarse FDTD grid is used outside this region. The advantage of the ADI-FDTD scheme is that it can be synchronized with the time marching step employed in the coarse FDTD scheme, obviating the need for the temporal interpolation of the fields in the process. This helps to render the hybrid ADI-FDTD subgridding scheme to be more efficient than the conventional FDTD subgridding algorithm in terms of the run time. The phase and attenuation constants of the dominant mode of a lossy stripline are computed by the proposed scheme to validate the technique View full abstract»

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  • Packaging technology for 40-Gb/s optical receiver module with an MU-connector interface

    Page(s): 429 - 433
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    A compact 40-Gb/s optical receiver module with an MU-connector interface has been developed. Its packaging has three main technical features. (1) Coplanar waveguide (CPW) patterns of the waveguide photodiode (WG-PD) and of the preamplifier IC in the facing area of the flip-chip structure are optimized for impedance matching. (2) A film carrier is used to connect the preamplifier IC to an electrical coaxial connector for electrical signal output. (3) An MU-connector is used as the optical interface to reduce the module size. Optimum design enabled a module size of 14.0 mm wide, 40.4 mm long, and 9.65 mm high. Measurements showed a 3-dB down bandwidth of the optical/electrical response of at least 50 GHz and a clear open eye pattern for a 40-Gb/s nonreturn-to-zero (NRZ) signal input. This optical receiver module is suitable for large-capacity communication network systems View full abstract»

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  • Single level integrated packaging modules for high performance electronic systems

    Page(s): 477 - 485
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    In this paper, we studied a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies toward single level integration. This new approach is an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Main benefits include very high performance, ultra high density, mixed-signal integration, and inexpensive. Several key technologies such as chip assembly and planarization were developed. A feasible fabrication procedure for single level integration has been established. Demonstrating modules were presented. Interconnect structures, signal and power distribution, and electrical performance were studied theoretically and experimentally for GHz off-chip operating. Properties of signal propagation and coupling from chip to chip were investigated both in frequency domain and in time domain by simulations and by high frequency measurements. The studies show that the new modules are capable of several Gb/s/pin data rate for off-chip communications. Besides, some design guidelines for best performance are obtained through the work View full abstract»

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  • High performance selectively oxidized VCSELs and arrays for parallel high-speed optical interconnects

    Page(s): 442 - 449
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    High-bandwidth single-mode selectively oxidized vertical-cavity surface-emitting laser (VCSEL) arrays operate at 980 nm or 850 nm emission wavelength for substrate or epitaxial side emission. Coplanar feeding lines and polyimide passivation are used to reduce electrical parasitics in top-emitting GaAs and bottom-emitting InGaAs VCSELs. To enhance fundamental single-mode emission for larger devices of reduced series resistance a surface relief transverse mode filter is employed. Fabricated VCSELs are applied in various interconnect schemes. InGaAs quantum-well based VCSELs at 935 nm emission wavelength are investigated for use in perfluorinated graded-index plastic-optical fiber (GI-POF) links. We obtain a 7 Gb/s pseudo random bit sequence (PRBS) nonreturn-to-zero (NRZ) data transmission over 80 m long 155 μm diameter GI-POF. We investigate data transmission over standard 1300 nm, 9 μm core diameter single-mode fiber with selectively oxidized single-mode GaAs and InGaAs VCSELs. We achieve biased 3 Gb/s and bias-free 1 Gb/s pseudo-random data transmission over 4.3 km at 830 nm emission wavelength where a simple fiber mode filter is used to suppress intermodal dispersion caused by the second order fiber mode. For the first time, we demonstrate 12.5 Gb/s data rate transmission of PRBS signals over 100 m graded-index multimode fiber or 1 km single-mode fiber using high performance single-mode GaAs VCSELs of 12.3 GHz modulation bandwidth emitting at λ=850 nm View full abstract»

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  • Flip chip on board solder joint reliability analysis using 2-D and 3-D FEA models

    Page(s): 499 - 506
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    This study investigates the effects of employing different two-dimensional (2-D) and three-dimensional (3-D) finite element analysis (FEA) models for analyzing the solder joint reliability performance of a flip chip on board assembly. The FEA models investigated were the 2-D-plane strain, 2-D-plane stress, 3-D-1/8th symmetry and 3-D-strip models. The different stress and strain responses generated by the four different FEA models were applied to various solder joint low cycle fatigue life prediction relationships. The investigation shows that the 2-D-plane strain and 2-D-plane stress models gave the highest and lowest solder joint strains, respectively. The 3-D-strip and 3-D-1/8th symmetry model results fall in between the 2-D-plane strain and 2-D-plane stress model results. The 3-D-1/8th symmetry model agrees better with the 2-D-plane strain model, while the 3-D-strip model agrees better with the 2-D-plane stress model results. The results for the fatigue life prediction analyses also show similar trends View full abstract»

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  • Empirical equations on electrical parameters of coupled microstrip lines for crosstalk estimation in printed circuit board

    Page(s): 521 - 527
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    Empirical equations for the self and mutual capacitance and inductance (Cs, Cm, Ls, Lm) of coupled microstrip lines in a printed circuit board were derived from the numerical simulation results to reduce the computation time for crosstalk estimation. Comparison of the measured Cs, Cm , Ls and Lm values with the derived empirical equations showed good agreements. Also in the near-end and far-end crosstalks, good agreements were obtained between measurements and the derived empirical equations. Microstrip lines embedded in the homogeneous dielectric material as well as those in the inhomogeneous medium with one side exposed to air were considered in this work. Based on the derived empirical equations, a design guide on the spacing between microstrip lines was established View full abstract»

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  • The evolution of passive devices in WDM networks

    Page(s): 590 - 594
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    The development of a variety of technologies has progressed over the last ten years to meet the demands for optical bandwidth in fiber-optics networks made available by wavelength division multiplexing (WDM). These technologies will be described and compared for their ability to fulfill optical functions. The role of currently developing technologies and devices for future networks is discussed. Methods of active control of passive devices are described to compensate for system changes. The increasing demands for lower costs and functionality are the motivation toward integration, automated assembly and versatility of technology View full abstract»

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  • Characterization of 63Sn37Pb and 80Au2OSn solder sealed optical fiber feedthroughs subjected to repetitive thermal cycling

    Page(s): 576 - 585
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    A highly accurate prediction of hermeticity lifetime is made for eutectic 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber-Kovar TM nosetube feedthroughs subjected to repetitive thermal cycling. Thermal fatigue fracture of the Sn-Pb solder/KovarTM interface develops when cracks, initially generated from creep deformation of the solder, propagate gradually through the junction in the axial direction. A nonlinear axisymmetric finite element analysis of the 63Sn37Pb fiber feedthrough seal is performed using a thermo-elastic creep constitutive equation, and solder joint fatigue based on accumulated strain energy associated with solder creep imposed by temperature cycling is analyzed. Additionally, thermal effective stress and plastic strain is studied for alternative 80Au20Sn solder by the finite element method with results indicating significant increase in useful life as compared to 63Sn37Pb. SEM/EDX metallurgical analysis of the solder/Ni-Au plated KovarTM nosetube interface indicates that AuSn4 intermetallic formed during soldering with 63Sn37Pb also contributes to joint weakening, whereas no brittle intermetallic is observed for 80Au20Sn. Hermetic carbon coated optical fibers metallized with Ni,P-Ni underplate and electrolytic Au overplating exhibit correspondingly similar metallurgy at the solder/fiber interface. Combined hermeticity testing and metallurgical analysis carried out on 63Sn37Pb and 80Au20Sn alloy solder sealed optical fiber feedthroughs after repetitive temperature cycling between -65 and +150°C, and -40 and +125°C validated the analytical approach View full abstract»

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  • Aging studies of PBGA solder joints reflowed at different conveyor speeds

    Page(s): 486 - 492
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    In this paper, the shear cycle fatigue properties of plastic ball grid array (PBGA) assemblies' solder joints reflowed with three different profiles, and aged at 125°C for four, nine, 16, 25, and 36 days are studied. The profiles were devised to have the same "heating factor," which was defined as the integral of the measured temperature above the liquidus (183°C) with respect to dwell time in the reflow profile, but to have different conveyor speeds. The effects of conveyor speed on the solder joint (nonaged and aged) fatigue lifetimes were investigated. It was found hat with increasing the conveyor speed the solder joint shear fatigue lifetime could be improved substantially. Also, the shear fatigue lifetimes of aged solder joints decreased with increasing aging time and variation in fatigue lifetimes increased for faster conveyor speed. SEM and optical micrographs show that faster cooling rate caused a rougher interface of solder/IMC and less crystallization microstructure in solder joints. Rougher interface solder joints have a longer nonaged fatigue life. The thickness of IMC increases with increasing aging time and the growth rate for solder with faster cooling rate was larger. SEM cross section views reveal that cracks initiated at the acute position near the solder pad, then propagated along the interface of the bulk solder/IMC layer. Thicker IMC layers deteriorated fatigue life, so the fatigue lifetime variation of aged solder joints with fast cooling rate was larger View full abstract»

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  • Methods for passive fiber chip coupling of integrated optical devices

    Page(s): 450 - 455
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    A useful technique for high precision passive coupling of single mode optical fibers to integrated optical devices is crucial for cost effective packaging especially in multiport devices like switches (N×N) and other WDM components. These devices were fabricated on two different material bases, silicon on insulator (SOI) and polymers. In both cases the waveguides are based on the oversized rib waveguide concept and utilize silicon as a substrate. Two possible fabrication processes for this passive fiber chip coupling IN or ON silicon are presented and compared. The first approach involves a technology similar to flip chip fabrication using a sub- and superstrate, that allows separate processing of v-grooves for fiber alignment and the integrated optical devices. The self aligned mounting of the chip is achieved by a v-shaped rib-groove combination created by wet chemical etching, where the rib is the exact negative of the groove so that the flip chip is put on precisely defined crystal planes rather than on sensitive edges, which would be the case when using rectangular alignment ribs. The second approach utilizes the same chip for waveguides and fiber alignment structures which makes it possible to define both in the same lithographic step and thereby eliminating any vertical displacement. Processing difficulties arise primarily from completely different processing requirements of fiber aligning v-grooves and integrated waveguides. The need to define patterns of the size of only several microns (μm) in the proximity to deep grooves makes the use of an electrophoretic photoresist necessary that is deposited via galvanic means on the extremely nonplanar surface. Both processes allow for fiber chip alignment precisions in the sub-μm range which was also experimentally verified with coupling losses as low as 0.7 dB per end-face. The fabrication processes along with experimental and theoretical results are presented View full abstract»

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  • Single mode fiber MT-RJ SFF transceiver module using optical subassembly with a new shielded silicon optical bench

    Page(s): 419 - 428
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    Demand for a compact cost reduced optical transceiver has arisen. Small form factor (SFF) optical transceivers are expected to meet this demand. A new concept optical module based on V-grooved silicon optical bench (SiOB) technology, that enables a passive alignment of optical fibers and optical devices is expected to reduce the cost. MT-RJ SFF optical transceivers require this new packaging technique because the distance between input and output optical axes is shorter than conventional transceivers. However, crosstalk between a transmitter and a receiver is a big issue to be solved because the distance between optical axes of the laser diode (LD) and the photo diode (PD) is only 0.75 mm. It is difficult to reduce the crosstalk in a SiOB because large electromagnetic coupling exists due to the conductivity of a silicon substrate. A newly developed, low crosstalk optical subassembly (OSA) with a single mode fiber MT-RJ receptacle and the SFF transceiver module are reported. We have analyzed a mechanism of electrical crosstalk in a SiOB and developed a shield structure to reduce it. The crosstalk in the OSA with shielded SiOB was reduced over 20 dB compared to the unshielded SiOB View full abstract»

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  • Mechanical deflection system (MDS) test and methodology for PBGA solder joint reliability

    Page(s): 507 - 514
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    A mechanical deflection system (MDS) was developed for highly accelerated tests to evaluate the solder joint fatigue performance in printed circuit board assemblies. The MDS test system can be used for design verification and qualification tests for solder joint reliability. Cyclic twisting deformation is imposed on an assembled printed circuit board (PCB) at isothermal conditions. The MDS test technique makes a significant contribution to reducing solder joint reliability testing cycle time. Fatigue performance of the PBGA solder joints subjected to the MDS test was investigated by three-dimensional finite element modeling. The solder joint fatigue lives were computed for several different MDS test conditions View full abstract»

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  • Effect of temperature cycling on joint strength of PbSn and AuSn solders in laser packages

    Page(s): 563 - 568
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    The effect of temperature cycle testing on the joint strength of PbSn and AuSn solders in laser diode packages has been studied experimentally and numerically. Experimental results showed that the joint strength increased as the temperature cycle number increased initially, and then became steady after 400 cycles. The joint strengths of PbSn and AuSn solders increased about 40% to 20% after undergoing 500 temperature cycles, respectively. A finite-element method (FEM) analysis was performed on the calculation of joint strength variation of PbSn and AuSn solders in temperature cycling tests. The coupled thermal-elasticity-plasticity model was employed in the solidification and residual stresses calculation. Simulation results were in good agreement with the experimental measurements that the solder joint strength increased as the temperature cycle increased. Numerical results indicate that the increasing solder joint strength comes from the redistribution of the residual stresses within the solder during temperature cycling tests. The local yielding and the creep effects on the low melting temperature solders will make uniform the residual stresses distribution introduced in the solidification process and increasing the solder joint strength as the temperature cycle number increased. The result suggests that the FEM is an effective method for analyzing and predicting the solder joint strength in laser diode packages View full abstract»

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  • Mounting of high power laser diodes on boron nitride heat sinks using an optimized Au/Sn metallurgy

    Page(s): 434 - 441
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    High power diode lasers have become more and more important to industrial and medical applications. In contrast to low power applications, long cavity lasers or laser bars are used in this field and mounting quality influences considerably laser performance and life time. In this paper we focus on the solder metallurgy and stress-induced laser behavior after mounting. The laser chips have been bonded fluxless epi-side down on translucent cubic boron nitride (T-cBN) using Au/Sn solder. The laser behavior has been tested with different chip metallizations preserving the eutectic solder composition or forming the Au rich ζ-phase during reflow. The resulting additional stress in the lasing region has been independently indicated by polarization measurements of the emitted light. A metallization scheme has been developed which forms the highly melting ζ-phase during soldering within a wide process window. This procedure yields better results then using eutectic Au/Sn which has a higher hardness than the ζ-phase. Laser diodes up to a cavity length of 2000 μm and an aperture of 200 μm have successfully been mounted on T-cBN. State of the art laser data, excellent thermal stability, high yield and reliability have been obtained View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering