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Solid-State Circuits, IEEE Journal of

Issue 2 • Date Feb. 2002

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Displaying Results 1 - 21 of 21
  • Editorial

    Page(s): 103
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    Freely Available from IEEE
  • New associate editor

    Page(s): 104
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    Freely Available from IEEE
  • Synchronization circuit performance

    Page(s): 202 - 209
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    Synchronizer circuits are usually characterized by their rate of failure in transmitting data between two independently timed regions. The mean time between failures (MTBF) is given. These effects can be explained by extending the existing theory to take account of initial offsets, and we propose a new, more accurate, formula. Synchronizer performance depends on achieving a high reliability of synchronization together with a short time. We show that commonly used circuits, such as the jamb latch, do not produce the best compromise for very high reliability applications, and that a better circuit can be designed. In order to confirm that thermal noise does not influence the MTBF against synchronization-time relationship, we have devised an experiment to measure noise in an integrated CMOS bistable circuit. We show that the noise exhibits a Gaussian distribution, and is close to the value expected from thermal agitation. View full abstract»

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  • Patent abstracts

    Page(s): 256 - 261
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    Freely Available from IEEE
  • A 100×100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding

    Page(s): 160 - 172
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    A 100×100 pixel analog very large scale integration retina is proposed to extract the magnitude and direction of spatial gradients contained in sensed images. The retina implements in a massively parallel fashion, at pixel level, an algorithm based on the concept of steerable filters to compute the gradients. An output rate of up to 1000 frames per second is achieved in a standard CMOS 0.5 μm process. The retina provides address-event coded output on two asynchronous buses, one dedicated to the the gradient's direction and another to the gradient's magnitude. The gradient information is temporally ordered from the largest to the smallest gradient's magnitude. Rationales for such an order are borrowed from information theory. Precise timing of the address events is controlled by a decreasing threshold function, whose slope can be dynamically modified to regulate the data flow on the communication bus so as to reduce the number of collisions. Quantitative experimental results from a fully functional silicon demonstrator are presented View full abstract»

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  • A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias

    Page(s): 210 - 217
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) scheme, the substrate bias is controlled so that delay in a circuit remains constant. The substrate bias is continuously changed from -1.5 V of reverse bias to 0.5 V of forward bias in order to compensate for fabrication-process fluctuation, supply-voltage variation, and operating-temperature variation. Advantages and disadvantages of substrate bias control with the forward bias are discussed. The SA-Vt CMOS scheme with forward bias is implemented in a 4.3M-transistor microprocessor. The controller occupies 320×400 μm in area and consumes 4-mA current. A 0.5-V forward bias raises the maximum operating frequency of the processor by 10%. The processor provides 400 VAX MIPS at 1.5-1.8 V supply with 320-380-mW power dissipation, that is, it achieves 1.2-GIPS/W performance View full abstract»

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  • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

    Page(s): 183 - 190
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    A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-μm microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3σ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations View full abstract»

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  • A field programmable analog array for CMOS continuous-time OTA-C filter applications

    Page(s): 125 - 136
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    A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade View full abstract»

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  • Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance

    Page(s): 218 - 227
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    An associative-memory architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified View full abstract»

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  • An ASIC for Hartmann-Shack wavefront detection

    Page(s): 173 - 182
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    An analog VLSI circuit facilitating the focal point position detection in a Hartmann-Shack wavefront sensor for optical wavefront measurements is presented. Detecting the lateral deviation of each focal point of the Hartmann-Shack sensor's lens array caused by the partial distortion of the aberrated wavefront within the according lens, the phase information of the light beam can be retrieved. With the future aim of measuring optical distortions of the human eye, the ASIC is optimized to process an optical incident power of 1 nW per focal point. To prevent spatial aliasing of the focal point positions due to the eye's inherent movements during measurement, the signal processing circuits are designed to allow frame repetition rates of wavefront measurement of several hundred hertz. Experimental measurements of optical lenses show the capability of the prototype ASIC of measuring focal point position deviations relating to spherical and cylindrical wavefront aberrations with a dynamic range of ±1 diopters at an accuracy of ±0.15 diopters. The incident power of 1 nW per focal point thereby allows integration periods of 1 ms for position detection View full abstract»

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  • Race logic architecture (RALA): a novel logic concept using the race scheme of input variables

    Page(s): 191 - 201
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (708 KB) |  | HTML iconHTML  

    A novel logic concept, Race Logic Architecture (RALA), is proposed. RALA is a new logic operation architecture in that the racing between input variables along the interconnection lines functions as an active logic element instead of logic gates, while the logic gates play a simple passive role. Logic operations of RALA are based on wired-OR that utilizes shared space and serial-AND that utilizes the triggering sequence of input variables. With these two concepts, RALA can implement arbitrary Boolean operations. Various kinds of combinational circuits are simulated and compared with RALAs. RALA shows the best performance in delay time, area, and power product results. A 64-bit carry-look-ahead adder with RALA is fabricated by 0.25-μm CMOS technology to verify its feasibility and functionality. The area of the adder is 800 μm×150 μm, and the delay time from the clock to Sum31 measured 0.9 ns View full abstract»

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  • Highly sensitive Hall magnetic sensor microsystem in CMOS technology

    Page(s): 151 - 159
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    A highly sensitive magnetic sensor microsystem based on a Hall device is presented. This microsystem consists of a Hall device improved by an integrated magnetic concentrator and new circuit architecture for the signal processing. It provides an amplification of the sensor signal with a resolution better than 30 μV and a periodic offset cancellation while the output of the microsystem is available in continuous time. This microsystem features an overall magnetic gain of 420 V/T View full abstract»

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  • A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme

    Page(s): 245 - 250
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    An equalizing transceiver was implemented by using a 0.35-μm CMOS technology for DRAM bus system. An equalization scheme was used in the receiver to reduce intersymbol interference (ISI). To maximize the data rate, a one-to-eight demultiplexing scheme was used in the equalizer of the receiver such that eight equalizers operate in parallel at the clock frequency, which is one-eighth the data rate. The maximum data rates were measured to be 840 Mb/s with twelve 5-pF capacitors connected in uniform spacing along a transmission line. The test criterion for successive transmission was set to the bit-error rate (BER) of 10-12 for the pseudorandom binary sequence (PRBS) data. The effectiveness of equalizers was demonstrated by measuring the BER with equalizers on and off, respectively. The chip size was 800×400 μm2 and the supply voltage was 3.3 V View full abstract»

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  • A 700-MHz 1-W fully differential CMOS class-E power amplifier

    Page(s): 137 - 141
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    A 700-MHz fully differential class-E CMOS power amplifier for wireless applications has been built toward maximum efficiency. The prototype can deliver 1 W of output power in a 50-Ω output impedance. The maximum power-added efficiency (PAE) is measured to be 62%. The obtained efficiency and output power is compared with the class-E amplifiers theory View full abstract»

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  • The effects of a ground shield on the characteristics and performance of spiral inductors

    Page(s): 237 - 244
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    The frequency dependence of the model parameters of patterned ground shield (PGS) inductors in large part is explained as a consequence of modeling a distributed system with a lumped model. The effects of PGS shape and material on inductor characteristics have been examined and explained. There is an optimum area for a PGS to maximize Q. Using an n+ buried/n-well PGS, the peak Q is improved by ~25% from that of an inductor without a PGS while only slightly changing L and Cp in comparison to inductors with other PGSs. Having a PGS does not significantly improve isolation between adjacent inductors when isolation is limited by magnetic coupling since a PGS is specifically designed to limit termination of magnetic fields View full abstract»

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  • A class-D vertical booster for CRT

    Page(s): 142 - 150
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    Integrated vertical boosters for the cathodic tube (CRT) are in charge of the vertical scanning of the electron beam on the CRT. They are amplifiers, and their function is to apply a sawtooth current on their load, which is a deflection yoke. The value of the current to be considered is typically around 2 A peak to peak. For such circuits in linear operating mode, the power dissipation is around 6 W in the integrated circuit for 2 W supplied to the load. The following circuit in class-D operating mode allows to reduce drastically the power dissipated in the integrated circuit and consequently the power consumption of the application. The power saving is typically 4 W compared with a traditional class-AB application. Taking in account the main power supply efficiency the total power saving is around 5 W View full abstract»

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  • On the use of Nauta's transconductor in low-frequency CMOS gm -C bandpass filters

    Page(s): 114 - 124
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    This paper discusses the use of a transconductor, first proposed by Nauta for high frequency applications, in low frequency CMOS gm -C bandpass filters. The behavior of the transconductor is examined in detail, showing that the robust implementation of higher-order low-voltage filters is possible for center frequencies in the lower megahertz region. The experimental results are presented of the realization of two prototypes, a 0.6-μm CMOS 18th-order real bandpass filter and a 0.35-μm CMOS 7th-order complex (14th-order bandpass) filter, both with a center frequency of 3 MHz and a passband of 1 MHz. These filters comply with the specifications for the channel-select stage of the Bluetooth short-range radio receiver View full abstract»

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  • A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology

    Page(s): 228 - 236
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    Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply View full abstract»

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  • An adaptive analog noise-predictive decision-feedback equalizer

    Page(s): 105 - 113
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    In this paper, an adaptive noise-predictive decision-feedback equalizer (NPDFE) is presented. The NPDFE architecture and its implementation are described. The NPDFE consists of an analog finite-impulse-response (FIR) forward equalizer, a recursive analog equalizer for noise prediction, and a decision-feedback equalizer (DFE). The recursive equalizer reduces noise enhancement and improves the signal-to-noise ratio (SNR) at the decision slicer input. The prototype targets a magnetic recording channel modeled by a Lorentzian impulse response. Measured results show that compared to a conventional DFE with FIR forward equalizer, the NPDFE achieves a SNR improvement of about 2 dB with PW50=2.5T. The NPDFE consumes 130 mW at a data rate of 100 Mb/s and occupies 1.3 mm2 of die area in a 0.5-μm CMOS process View full abstract»

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  • A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs

    Page(s): 251 - 254
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    A bipolar-voltage programmable antifuse circuit scheme and bit-repair scheme are newly proposed for post package repair. For fail-bit repair, the antifuses in the proposed scheme are programmed by bipolar voltages of VCC and -VCC, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair scheme, reducing the layout area for the redundancy bits. Also, using static latches instead of dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust and avoiding burn-in stress issues. Through manufacturing commercial DRAM products, the yield improvement by the one-bit post-package repair reaches as much as 2.4% for 0.16-μm triple-well 256-M SDRAM View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan