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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb 2002

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Displaying Results 1 - 20 of 20
  • Flicker noise in gate overlapped polycrystalline silicon thin-film transistors

    Publication Year: 2002 , Page(s): 319 - 323
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    A study of the noise performance of gate overlapped polycrystalline silicon thin-film transistors (TFTs) is presented. Low-frequency noise measurements were carried out on n- and p-type samples fabricated by excimer laser crystallization. It is shown that the carrier number fluctuation model applies not only to n-type but also to p-type devices. The density of oxide traps was extracted from the noise measurements and was of the order of 1018-1019 eV-1 cm-3 View full abstract»

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  • Sub-ft gain resonance of InP/InGaAs-HBTs

    Publication Year: 2002 , Page(s): 213 - 220
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    Advanced npn-InP/InGaAs HBTs are often operated at high current levels for optimum high-speed performance. Because of velocity modulation effects, these transistors may operate in base-pushout although measurements of the cut-off frequency ft indicate the opposite. We show that the low mobility of the holes has a strong effect on the transistor operation in this regime, which is only revealed from a dynamic analysis: The unilateral power gain peaks far below ft followed by a -40 dB/dec roll-off. The effect was thoroughly analyzed and as a result, we present a simple equivalent circuit model that successfully describes transistors operating in pushout up to very high frequencies View full abstract»

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  • Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

    Publication Year: 2002 , Page(s): 308 - 313
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (155 KB)  

    Threshold voltage (Vt) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-μm single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N2 implant prior to gate oxidation is important to reduce Vt roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving Vt roll-off characteristics. Finally, the impact of halo implant on Vt variation in sub-0.2-μm buried channel pFETs is discussed. It is found that halo profile control is necessary for tight Vt variation in sub-0.2-μm single workfunction gate pFET View full abstract»

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  • High breakdown characteristic δ-doped InGaP/InGaAs/AlGaAs tunneling real-space transfer HEMT

    Publication Year: 2002 , Page(s): 221 - 225
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB) |  | HTML iconHTML  

    A novel δ-doped InGaP/InGaAs/AlGaAs tunneling real-space transfer high-electron mobility transistor (TRST-HEMT) has been successfully fabricated by low-pressure metal organic chemical vapor deposition (LP-MOCVD). Three-terminal N-shaped negative differential resistance (NDR) phenomenon due to the hot electrons real-space transfer (RST) at high electric field is observed. Two-terminal gate-to-drain breakdown voltage is more than 40 V with a leakage current as low as 0.27 mA/mm. High three-terminal on-state breakdown voltage as high as 19.2 V and broad plateau of current valley as high as 15 V are achieved. These characteristics are attributed to the use of high Schottky barrier height, high bandgap of InGaP Schottky layer, δ-doping, and GaAs subspacer layers. The measured maximum peak-to-valley ratio (PVR) value is 2.7 View full abstract»

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  • A new compact DC model of floating gate memory cells without capacitive coupling coefficients

    Publication Year: 2002 , Page(s): 301 - 307
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    This paper presents for the first time a new compact SPICE model of floating gate nonvolatile memory cells capable to reproduce effectively the complete DC electrical behavior in every bias conditions. This model features many advantages compared to previous ones: it is simple and easy to implement since it uses SPICE circuit elements, is scalable, and its computational time is not excessive. It is based on a new procedure that calculates the floating gate voltage without using fixed capacitive coupling coefficients, thus improving the floating gate voltage estimate that is fundamental for the correct modeling of cell operations. Moreover, this model requires only the usual parameters adopted for SPICE-like models of MOS transistors plus the floating gate-control gate capacitance, making it very attractive to industry as the same parameter extraction procedure used for MOS transistors can be directly applied. The model we propose has been validated on E2PROM and flash memory cells manufactured in existing technology (0.35 μm and 0.25 μm) by STMicroelectronics View full abstract»

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  • Linear cofactor difference method of MOSFET subthreshold characteristics for extracting interface traps induced by gate oxide stress test

    Publication Year: 2002 , Page(s): 331 - 334
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    A new subthreshold analysis technique, the linear cofactor difference method, is presented in this brief for extraction of the MOSFET interface traps induced by the gate oxide stress test. This technique relies on new linear cofactor difference extreme spectral characteristics of MOSFET gate voltage in the subthreshold region. It is shown that this method enables reliable extraction of the increased interface traps with a rise of the accumulated gate oxide stress test time to be obtained and that its validity is also verified by the extraction experiments on an n-channel MOSFET (nMOST) device View full abstract»

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  • Ambipolar Schottky-barrier TFTs

    Publication Year: 2002 , Page(s): 264 - 270
    Cited by:  Papers (1)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    A novel Schottky-barrier metal-oxide-semiconductor thin-film transistor (SBTFT) was successfully demonstrated and characterized. The new SBTFT device features a field-induced-drain (FID) region, which is controlled by a metal field-plate lying on top of the passivation oxide. The FID region is sandwiched between the silicided drain and the active channel region. Carrier types and the conductivity of the transistor are controlled by the metal field-plate. The device is thus capable of ambipolar operation. Excellent ambipolar performance with on/off current ratios over 106 for both p- and n-channel operations was realized simultaneously on the same device fabricated with polysilicon active layer. Moreover, the off-state leakage current shows very weak dependence on the gate-to-drain voltage difference with the FID structure. Finally, the effects of FID length are explored View full abstract»

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  • A novel approach for focusing electron beams using low-cost ceramic grid [field emitter arrays]

    Publication Year: 2002 , Page(s): 324 - 328
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB) |  | HTML iconHTML  

    A low-cost ceramic grid was used as a stand-alone focusing electrode in field emitter arrays to obtain high brightness and small electron beam size. The ceramic grid with an array of 200-μm holes was made from DuPont 591 with low-cost equipment. Beam size is controllable by the voltage applied to the focusing grid. Light intensity profiles were measured and analyzed. The full width at half maximum (FWHM) of the light profile excited by electron emission from 30-μm wide field emitter arrays is 60 μm at 5000 V with 6 mm anode-cathode separation. At an anode voltage of 2000 V and gate voltage of 55 V, focusing is optimized at a focusing voltage of 30 V. Arc-free operation at 10 kV was achieved, thereby promoting improved phosphor efficiency. This focusing approach may lead to improve lifetimes for field emission displays and other vacuum microelectronic devices by significantly increasing the total vacuum volume and providing a means for improved getter utilization View full abstract»

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  • Transparent and quasi-transparent regional solutions to minority-carrier transport in arbitrarily doped semiconductors

    Publication Year: 2002 , Page(s): 329 - 331
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (94 KB) |  | HTML iconHTML  

    The exact analytical regional solution to minority-carrier transport is derived in arbitrarily doped transparent semiconductor regions. By using this solution, new regional quasi-transparent solutions for emitter light-generated current density are derived in both the Cuevas and Balbuena approach (Cuevas and Balbuena, IEEE Trans. Electron Devices, vol. 36, pp. 553-560, 1989) and the Hamel approach (Hamel, IEEE Trans. Electron Devices, vol. 46, pp. 104-109, 1996) . Either of the new third-order quasi-transparent expressions is shown to be more accurate than both the local second-order quasi-transparent expression of Cuevas and Balbuena and the third-order regional expression of Bisschop et al (IEEE Trans. Electron Devices, vol. 37, pp. 358-364, 1990). In particular, while the new expression derived according to Hamel is more accurate at passivated surfaces, the new expression derived according to Cuevas and Balbuena is always more accurate, except for the case of a negligible surface recombination, where it is as accurate as the third-order regional expression of Bisschop et al View full abstract»

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  • A 0.2-μm 180-GHz-fmax 6.7-ps-ECL SOI/HRS self-aligned SEG SiGe HBT/CMOS technology for microwave and high-speed digital applications

    Publication Year: 2002 , Page(s): 271 - 278
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    A technology for combining 0.2-μm self-aligned selective-epitaxial-growth (SEG) SiGe heterojunction bipolar transistors (HBTs) with CMOS transistors and high-quality passive elements has been developed for use in microwave wireless and optical communication systems. The technology has been applied to fabricate devices on a 200-mm SOI wafer based on a high-resistivity substrate (SOI/HRS). The fabrication process is almost completely compatible with the existing 0.2-μm bipolar-CMOS process because of the essential similarity of the two processes. SiGe HBTs with shallow-trench isolations (STIs) and deep-trench isolations (DTIs) and Ti-salicide electrodes exhibited high-frequency and high-speed capabilities with an fmax of 180 GHz and an ECL-gate delay of 6.7 ps, along with good controllability and reliability and high yield. A high-breakdown-voltage HBT that could produce large output swings for the interface circuit was successfully added. CMOS devices (with gate lengths of 0.25 μm for nMOS and 0.3 μm for pMOS) exhibited excellent subthreshold slopes. Poly-Si resistors with a quasi-layer-by-layer structure had a low temperature coefficient. Varactors were constructed from the collector-base junctions of the SiGe HBTs. MIM capacitors were formed between the first and second metal layers by using plasma SiO2 as an insulator. High-Q octagonal spiral inductors were fabricated by using a 3-μm thick fourth metal layer View full abstract»

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  • Ultralow resistance W/poly-Si gate CMOS technology using amorphous-Si/TiN buffer layer

    Publication Year: 2002 , Page(s): 295 - 300
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 Ω/sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by large grain size tungsten on an amorphous-silicon (a-Si) film. This result can be explained by the Mayadas-Shatzkes theory. After a source/drain annealing process, W/a-Si/TiN/pn-poly-Si systems become W/WSix/TiN/pn-poly-Si systems without impurity interdiffusion between the pn-poly-Si gate electrodes. The propagation delay time of a CMOS inverter ring oscillator with this novel gate electrode is considerably smaller than that with a cobalt-salicide film in a wider channel width View full abstract»

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  • Large-area lateral p-i-n photodiode on SOI

    Publication Year: 2002 , Page(s): 334 - 336
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (87 KB) |  | HTML iconHTML  

    Results of a large-area, low-capacitance lateral p-i-n photodiode in silicon-on-insulator (SOI) are presented. This photodiode possesses an antireflection coating optimized for blue light and is therefore appropriate for scintillation detector applications. An average external quantum efficiency of 78.6% and 68.4% is achieved for λ=430 nm and 400 nm, respectively. The rise and fall times of the lateral p-i-n photodiode for light with a wavelength of 400 nm are 9.7 ns and 11.2 ns, respectively. The capacitance of the SOI p-i-n photodiode is 0.72 pF/mm 2. This photodiode combines a high quantum efficiency and a low capacitance with a high speed View full abstract»

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  • Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs

    Publication Year: 2002 , Page(s): 287 - 294
    Cited by:  Papers (94)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    A compact physics-based quantum-effects model for symmetrical double-gate (DG) MOSFETs of arbitrary Si-film thickness is developed and demonstrated. The model, based on the quantum-mechanical variational approach, not only accounts for the thin Si-film thickness dependence but also takes into account the gate-gate charge coupling and the electric field dependence; it can be used for FDSOI MOSFETs as well. The analytical solutions, verified via results obtained from self-consistent numerical solutions of the Poisson and Schrodinger equations, provide good physical insight with regard to the quantization and volume inversion due to carrier confinement, which is governed by the Si-film thickness and/or the transverse electric field. A design criterion for achieving beneficial volume-inversion operation in DG devices is quantitatively defined for the first time. Furthermore, the utility of the model for aiding optimal DG device design, including exploitation of the volume-inversion benefit to carrier mobility, is exemplified View full abstract»

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  • Characterization of deep levels in Pt-GaN Schottky diodes deposited on intermediate-temperature buffer layers

    Publication Year: 2002 , Page(s): 314 - 318
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (81 KB) |  | HTML iconHTML  

    Gallium nitride (GaN)-based Schottky junctions were fabricated by RF-plasma-assisted molecular beam epitaxy (MBE). The GaN epitaxial layers were deposited on novel double buffer layers that consist of a conventional low-temperature buffer layer (LTBL) grown at 500°C and an intermediate-temperature buffer layer (ITBL) deposited at 690°C. Low-frequency excess noise and deep level transient Fourier spectroscopy (DLTFS) were measured from the devices. The results demonstrate a significant reduction in the density of deep levels in the devices fabricated with the GaN films grown with an ITBL. Compared to the control sample, which was grown with just a conventional LTBL, a three-order-of-magnitude reduction in the deep levels 0.4 eV below the conduction band minimum (Ec) is observed in the bulk of the thin films using DLTFS measurements View full abstract»

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  • SILC as a measure of trap generation and predictor of TBD in ultrathin oxides

    Publication Year: 2002 , Page(s): 226 - 231
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB) |  | HTML iconHTML  

    The theoretical basis of stress-induced leakage current (SILC) as a measure of bulk trap density within thin oxide films is explored. Contrary to popular belief, this measure is neither absolute, nor do most papers in the literature sufficiently specify the measurement conditions to make their comparison meaningful. We also explore the relationship between SILC generation rate and the time-to-breakdown, and show that only a very specific definition of SILC generation can capture the voltage dependence of the time-to-breakdown View full abstract»

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  • Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

    Publication Year: 2002 , Page(s): 279 - 286
    Cited by:  Papers (12)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (194 KB) |  | HTML iconHTML  

    Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si0.7Ge0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel View full abstract»

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  • On interface and oxide degradation in VLSI MOSFETs. II. Fowler-Nordheim stress regime

    Publication Year: 2002 , Page(s): 254 - 263
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    For pt. I see ibid., vol. 49, pp. 247-53 (2002).The assessment of the physical mechanisms governing the degradation of thin oxides is a very important and, unfortunately, elusive issue that has raised significant debate in recent literature. In this paper, we first use some of the results reported in Pt. I to estimate a reasonable boundary for the efficiency of a possible hydrogen release (HR) mechanism and argue that the HR appears too weak to explain our measurements of stress-induced leakage current (SILC) produced by Fowler-Nordheim (FN) tunneling stress measurements. Then, we present an in-depth investigation of the anode hole injection (AHI) mechanism at low stress gate voltages (VG). To this purpose, we used both previously discussed and ad hoc devised characterization techniques. Our results indicate that AHI is still operative at VG lower than previously experimentally demonstrated. Furthermore, the correlation between the energy of holes at the anode, their injection into the oxide, and the eventual generation of SILC strongly indicate that AHI is the mechanism governing oxide degradation in the considered stress conditions View full abstract»

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  • On interface and oxide degradation in VLSI MOSFETs. I. Deuterium effect in CHE stress regime

    Publication Year: 2002 , Page(s): 247 - 253
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    This paper analyzes in detail the generation of interface states (Nit) and stress-induced leakage current (SILC) during channel hot electron (CHE) stress experiments in the context of a possible hydrogen/deuterium (H/D) isotope effect. Our results show that Nit generation is related to the hydrogen release (HR) at the Si-SiO2 interface at relatively high VG where a large isotope effect is found. Instead, for gate voltages (VG) favorable for hot hole injection (HHI) the Nit creation becomes a unique function of hole fluence and the isotope effect disappears. In the studied stress conditions, we found no experimental evidence supporting a causal relation between SILC generation and HR because no isotope effect is observed even when the corresponding Nit measurements reveal a very different D/H release rate. Similar to Nit generation, we found that SILC becomes a unique function of hole fluence at low stress VG. Relevant implications and extensions of these results to the Fowler-Nordheim (FN) tunneling stress conditions are discussed in Pt. II View full abstract»

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  • A study of soft and hard breakdown - Part II: Principles of area, thickness, and voltage scaling

    Publication Year: 2002 , Page(s): 239 - 246
    Cited by:  Papers (27)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    For Part I see ibid., vol.49, no.2, pp.232-8 (2002). Based on the theory of soft and hard breakdown established in Part I of this paper, we now study the principles of area, thickness, voltage, and circuit configuration dependence of hard and soft breakdown. These scaling principles allow us to conclude that breakdown in ultrathin oxides stressed at operating voltages (1.0-1.5 V) can never be hard, which should allow a more relaxed reliability specification for these oxides View full abstract»

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  • A study of soft and hard breakdown - Part I: Analysis of statistical percolation conductance

    Publication Year: 2002 , Page(s): 232 - 238
    Cited by:  Papers (32)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB) |  | HTML iconHTML  

    A theory of the statistical origin of soft and hard breakdown, that can explain a wide range of experimental data, is proposed. The theory is based on the simple premise that the severity of breakdown depends on the magnitude of the power dissipation through the sample-specific, statistically distributed percolation conductance, rather than on any physical difference between the traps involved. This model (a) establishes the connection between the statistical distribution of the theoretically predicted percolation conductance and the distribution of experimentally measured conductances after soft breakdown (Part I), and (b) explains the thickness, voltage, stress, and circuit configuration dependence of soft and hard breakdown (Part II). Connections to previous theories are made explicit, and contradictions to alternate models are resolved View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego