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Circuits, Devices and Systems, IEE Proceedings -

Issue 6 • Date Dec 2001

 This issue contains several parts.Go to:  Part Supplement 

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Displaying Results 1 - 11 of 11
  • Impact of 0.25 μm dual gate oxide thickness CMOS process on flicker noise performance of multifingered deep-submicron MOS devices

    Publication Year: 2001 , Page(s): 312 - 317
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (514 KB)  

    The flicker noise performance of 0.25 μm thin gate oxide transistors from the dual gate oxide thickness process and the single gate oxide thickness process have been evaluated and compared. A total of 20 transistors have been measured. The results reveal that thin gate oxide transistors from the dual gate oxide thickness process show a maximum of an order reduction in the current noise spectra. This reduction can be attributed to the lower nitrogen concentration peak at the Si/SiO2 interface. Hence the dual gate oxide thickness process will be the state-of-the-art for the implementation of system-on-chip designs. In general, the low-frequency noise behaviour of the fabricated deep-submicrometre MOSFETs is best described by the number fluctuation with the correlated mobility fluctuation model View full abstract»

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  • Comments on "CMOS differential difference current conveyors and their applications"

    Publication Year: 2001 , Page(s): 335 - 336
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    For original paper see ibid., vol. 143, no. 2, p. 91-96 (1996 ). Recently Chiu, Liu, Ivan and Chen introduced a new active building block called a differential difference current conveyor (DDCC) and demonstrated its application in realising squarer, square rooter and multiplier circuits, differential integrators, and voltage mode (VM) and current mode (CM) low-pass/band-pass (LP/BP) filters. CMOS integrable implementations for DDCC+ and DDCC- (two separate circuits) were also proposed. This comment extends the domain of application of the DDCC to the realisation of CM all grounded passive elements (AGPE) SRCOs, not discussed by Chiu et al. or anyone else so far. In particular, we show that, if instead of considering DDCC+ and DDCC- as separate units, we consider a single unit which we call a differential difference complementary current conveyor (DDCCC), then such a DDCCC turns out to be a versatile device to implement CM AGPE SRCOs View full abstract»

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  • PI force control of a microgripper for assembling biomedical microdevices

    Publication Year: 2001 , Page(s): 348 - 352
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (543 KB)  

    Recent work is presented on the control of a microgripper based on flexure joints, fabricated by LIGA and instrumented with force sensors. The force sensors are semiconductor strain gauges which have been integrated in the microgripper and experimentally characterised. The microgripper is the core component of a workstation developed to grasp and manipulate tiny objects, such as components of biomedical microdevices. A proportional integral (PI) force control of the microgripper has been implemented. The results of the tracking experiments prove that this control algorithm can assure performance suitable for the intended applications View full abstract»

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  • Efficient ABR service engine for ATM networks

    Publication Year: 2001 , Page(s): 323 - 327
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (485 KB)  

    Considerable efforts have been focused on the available bit rate (ABR) service, which enables maximal link utilisation in the ATM network. An ABR service engine is presented, which provides optimal hardware solution for all functions of the ABR service algorithm. To compute congestion control information, the ABR service engine consists of an ER engine, a queueing connection (QC) estimation unit, and a cell decoder/encoder (CDE). To implement the algorithm efficiently, the new engine uses the following schemes. The ER is periodically computed in order to provide sufficient computation time. Through a periodical computation, a low cell delay is achieved when cells pass through the ABR service engine. Using a QC corrector, the implementation of the QC estimation unit is simplified. A register control block efficiently controls internal variables, and arithmetic units are designed for precise computation with simple architecture. Therefore, the ABR service engine is very small in size and provides high speed. In addition, it realises the computation of the congestion control information without a cell delay View full abstract»

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  • High-voltage smart power integrated circuits to drive piezoceramic actuators for microrobotic applications

    Publication Year: 2001 , Page(s): 343 - 347
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (570 KB)  

    The development of microrobots is very important in fields where sub-micrometre precision is required. An integrated driving solution based on a commercial BCD (bipolar, CMOS, DMOS) technology is proposed to implement proper drivers for microrobots formed by smart piezoactuator units (SPU). The high voltage signals that demand these actuators are performed by a driver based on a full custom design of a high voltage operational amplifier connected in the inverter configuration. They are able to supply a 50 V sinusoidal waveform at frequencies ranging about 10 kHz with the distortion levels appropriate to the application View full abstract»

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  • Simultaneous switching noise analysis and low-bounce buffer design

    Publication Year: 2001 , Page(s): 303 - 311
    Cited by:  Papers (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (663 KB)  

    An accurate equation to estimate simultaneous switching noise (SSN) created by CMOS output buffers is proposed. This analytic equation includes the carrier velocity saturation effects of a short-channel MOS transistor. Simulation results show that the proposed closed-form equation estimates the SSN precisely and the error is below 10% as compared with HSPICE simulation results. Design procedures of a low-bounce tapered buffer which take SSN into consideration are also proposed. Several output buffer design examples are demonstrated to show the significant improvement of the low-bounce buffer design. A test chip of the output buffer is implemented to operate at 400 MHz and the measurement results match the design specifications View full abstract»

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  • Development of an electromagnetic micro-generator

    Publication Year: 2001 , Page(s): 337 - 342
    Cited by:  Papers (35)  |  Patents (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (799 KB)  

    A design methodology for linear micro-generators is developed, and is applied to the design of a mm-scale electromagnetic micro-generator. The fabrication of a prototype device is also described using generally available microfabrication techniques, and the results of testing the device on a variable amplitude vibration source, in air and vacuum, are presented. The experimental results confirm the design rules and indicate how the generation of useful power levels might be achieved View full abstract»

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  • Fast and simple method to find all equilibrium points of dynamic 1-D arrays

    Publication Year: 2001 , Page(s): 328 - 334
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (542 KB)  

    A very fast and simple algorithm for finding all equilibrium points of dynamic one-dimensional (1-D) arrays, constituted by resistively coupled dynamic piecewise-linear cells (for example, oscillators), is presented. This algorithm is based oil the recursive construction of a uni-path V-I characteristic derived from the associated resistive array, obtained by opening the capacitors and shortening the inductors within dynamic cells. Some examples show the efficiency of the algorithm. About 30000 equilibrium points of a 100-cell array are determined within a few seconds with a common PC View full abstract»

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  • New CMOS 2 V low-power IF fully differential Rm-C bandpass amplifier for RF wireless receivers

    Publication Year: 2001 , Page(s): 318 - 322
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    A new CMOS fully differential bandpass amplifier (BPA) based on the structure of a transresistance (Rm) amplifier and capacitor is proposed and analysed. In this design, the Rm amplifier is realised by a simple inverter with tunable shunt-shunt feedback MOS resistor and tunable negative resistance realised by cross-coupled MOS transistors in parallel with a current source. The capacitor is in series with the input of the Rm amplifier, which realises the filter function and blocks the DC voltage. Under a 2 V supply voltage, the post-tuning capability of the gain can be as high as 55 dB whereas the tunable frequency range is 41-178 MHz. The power consumption is 14 mW and the dynamic range (DR) is 50 dB. The differential-mode gain is 20 dB and the common-mode gain is -25 dB so that the CMRR is 45 dB. Simple structure, good frequency response and low power dissipation make the proposed bandpass amplifier quite feasible for application in the IF stage of RF receivers View full abstract»

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  • Steady-state prediction in nonlinear circuits with periodic inputs by wavelet transform

    Publication Year: 2001 , Page(s): 296 - 302
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (438 KB)  

    The paper describes a method to predict steady states from transient states in nonlinear circuits with periodic inputs. The possibility of steady-state prediction from the transient state is shown if the wavelet transform is properly used. The discrete wavelet transform makes clear the variation of phase and frequency for characterising transient waveforms if the circuit has periodic inputs and the target for prediction is periodic. Additionally, a method is proposed to improve the time resolution, and the effects confirmed by an example View full abstract»

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  • Efficient algorithm to calculate Reed-Muller expansions over GF(4)

    Publication Year: 2001 , Page(s): 289 - 295
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (561 KB)  

    A new algorithm to generate the full polarity matrix of fixed polarity Reed-Muller expansions over Galois fields of order 4, GF(4), has been developed. By using directly the truth vector of the original function, a recursive formula is developed to generate the whole polarity matrix. The algorithm uses the properties of the fixed polarity matrix to speed up the calculation and reduce the number of necessary multipliers and adders. The computational complexity of the algorithm is compared with other works. It is shown that, for practical hardware implementations of quaternary functions, the new algorithm is better than all other existing algorithms. The fast flow diagrams for computation of the whole or partial matrix are also presented View full abstract»

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