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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 2 • Date Feb. 2002

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Displaying Results 1 - 10 of 10
  • Shortest path search using tiles and piecewise linear cost propagation

    Page(s): 145 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    In this paper we propose a new algorithm for finding shortest paths in a tile connection graph. This algorithm uses an exact piecewise linear cost model to guide our search of the compact tile graph. Unlike previous tile search algorithms, this algorithm always rinds a shortest path. Unlike the grid graph algorithms (which do find shortest paths), this algorithm searches the tile graph which is much smaller than the grid graph. The efficiency of our new approach is confirmed by our experiments comparing our new algorithm with the grid graph algorithms. View full abstract»

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  • A graph theoretic approach for synthesizing very low-complexity high-speed digital filters

    Page(s): 204 - 216
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (366 KB)  

    We present computation reduction techniques which can either be used to obtain multiplierless implementation of finite impulse response (FIR) digital filters or to further improve multiplierless implementation obtained by currently used techniques. Although presented in the FIR filtering framework, these ideas are also directly applicable to any task/application which can be expressed as multiplication of vectors by scalars. The presented approach is to remove computational redundancy by reordering computation. The reordering problem is formulated using a graph in which vertices represent coefficients and edges represent resources required in a computation using the differential coefficient defined by the difference of the vertices joined by the edge. This interpretation leads to various methods for computation reduction for which simple polynomial run time algorithms are presented. It is shown that about 20% reduction in the number of add operations per coefficient can be obtained over the conventional multiplierless implementations. It is also shown that implementations requiring less than one adder per coefficient can be obtained using the presented approaches when using nonuniformly scaled coefficients quantized from infinite precision representation by simple rounding View full abstract»

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  • DTT: direct truncation of the transfer function - an alternative to moment matching for tree structured interconnect

    Page(s): 131 - 144
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (278 KB)  

    A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reduced-order transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The method is numerically accurate for any order of approximation, which permits approximations to be determined with a large number of poles appropriate for approximating RLC trees with underdamped responses. The method is computationally efficient with a complexity linearly proportional to the number of branches in an RLC tree. A common set of poles is determined that characterizes the responses at all of the nodes of an RLC tree which further enhances the computational efficiency. Stability is guaranteed by the DTT method for low-order approximations with less than five poles. Such low-order approximations are useful for evaluating monotone responses exhibited by RC circuits View full abstract»

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  • Hierarchical analysis of power distribution networks

    Page(s): 159 - 168
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size View full abstract»

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  • Retiming and clock scheduling for digital circuit optimization

    Page(s): 184 - 203
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (557 KB) |  | HTML iconHTML  

    This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimization problems are explored: (1) clock period minimization and (2) tolerance maximization to clock-signal delay variations. Exact mixed-integer linear programming formulations and efficient heuristics are given for both problems. When both long and short paths are considered, circuits optimized by the combined application of retiming and clock scheduling can achieve shorter clock periods or demonstrate greater tolerance to clock-signal delay variations than circuits optimized by retiming or clock scheduling. Experiments with benchmark circuits demonstrate the effectiveness of the combined optimization. In comparison with the best result obtained by either of the two optimizations, the joint application of retiming and clock scheduling increased operating speeds by more than 8% on the average. It also increased tolerance to clock delay variations by an average of 12% over a broad range of target clock frequencies. Larger relative improvements were achieved for shorter clock periods, thus suggesting that simultaneous retiming and clock scheduling can play an important role in high-speed design View full abstract»

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  • Thorough testing of any multiport memory with linear tests

    Page(s): 217 - 231
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB) |  | HTML iconHTML  

    The quality of tests, in terms of fault coverage and test length, is strongly dependent on the used fault models. This paper presents realistic fault models for multiport memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ..., p-port faults. In addition, the paper discusses the test procedure for such memories; it shows that the time complexity of the required tests is not exponential proportionally with p, as published by different authors, but it is linear, irrespective of the number of ports of which the multiport memory consists View full abstract»

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  • Reporting of standard cell placement results

    Page(s): 240 - 247
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (111 KB)  

    Very large scale integration (VLSI) fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement approaches is crucial to the development of improved automation tools; unfortunately, publicly available placement benchmarks are outdated, and there are wide variations in their interpretation. In addition, the metrics considered by some academic research have questionable relevance to modern design. At best, poor benchmarks and differences in interpretation result in misunderstandings of the effectiveness of some approaches. At worst, they can motivate research in areas of very little promise, while other areas which have true potential are ignored. In this paper, we expand on work previously presented, describing current standard cell placement benchmarks and illustrating common differences in their interpretation. We also propose specific interpretation methods for traditional objectives, and discuss new metrics which should be considered in modern placement research. Our hope is that by presenting these issues clearly, we can enable more accurate evaluations of placement methods, and improve research efficiency View full abstract»

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  • An Esterel compiler for large control-dominated systems

    Page(s): 169 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB) |  | HTML iconHTML  

    Embedded hard real-time software systems often need fine-grained parallelism and precise control of timing, things typical real-time operating systems do not provide. The Esterel language has both, but compiling large Esterel programs has been challenging, producing either needlessly slow or large code. This paper presents the first Esterel compiler able to compile large Esterel programs into fast, small code. By choosing a concurrent control-now graph (CCFG) as its intermediate representation, it preserves many of the control constructs to produce code that can be 100 times faster and half the size than code from other compilers with similar capacity. The primary contribution is an algorithm that generates efficient sequential code from a CCFG. While developed specifically for compiling Esterel, the algorithm could be used to compile other synchronous languages with fine-grained parallelism View full abstract»

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  • Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions

    Page(s): 109 - 130
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (511 KB)  

    This paper presents a design flow for timed asynchronous circuits. It introduces lazy transitions systems as a new computational model to represent the timing information required for synthesis. The notion of laziness explicitly distinguishes between the enabling and the firing of an event in a transition system. Lazy transition systems can be effectively used to model the behavior of asynchronous circuits in which relative timing assumptions can be made on the occurrence of events. These assumptions can be derived from the information known a priori about the delay of the environment and the timing characteristics of the gates that will implement the circuit. The paper presents the necessary conditions to generate circuits and a synthesis algorithm that exploits the timing assumptions for optimization. It also proposes a method for back-annotation that derives a set of sufficient timing constraints that guarantee the correctness of the circuit View full abstract»

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  • Domino logic synthesis based on implication graph

    Page(s): 232 - 240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized automatic test pattern generation (ATPG)-based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on the implication graph can reduce transistor counts by 25% on average, while the delay increases less than 3% View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu