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Design & Test of Computers, IEEE

Issue 1 • Date Jan/Feb 2002

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Displaying Results 1 - 7 of 7
  • Cost-effective deterministic partitioning for rapid diagnosis in scan-based BIST

    Page(s): 42 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (141 KB)  

    Identifying fault-embedding scan cells is a significant challenge for fault diagnosis in scan based BIST. Deterministic partitioning techniques provide cost-effective solutions to this problem. Both mathematical solutions and simulations on hardware implementations demonstrate the effectiveness of these techniques View full abstract»

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  • Analyzing and diagnosing interconnect faults in bus-structured systems

    Page(s): 54 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB)  

    Testing multimodule systems presents several challenges, particularly when systems use submicron technology. The authors propose strategies to diagnose interconnect faults in bus-structured systems using several models. We propose several methods and strategies for a diagnosis using different fault models, including those applicable to submicron technology. Besides defining new features, such as the logical extent of faults, we also propose a reduction strategy that permits 100% fault detection and identification (including fault location) View full abstract»

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  • Modeling the economics of testing: a DFT perspective

    Page(s): 29 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy's impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT's impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don't consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies View full abstract»

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  • A complete strategy for testing an on-chip multiprocessor architecture

    Page(s): 18 - 28
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    The article proposes an approach that divides testing into three phases: router testing, RAM block testing, and distributed processor testing. This test strategy was implemented for the on-chip multiprocessor architecture of a fine-grain, massively parallel machine developed in 1995 at the National Polytechnic Institute of Grenoble. The hierarchical strategy minimizes the entire architecture's test cost by avoiding unnecessary testing. For example, testing a processor that is inaccessible because its router is faulty or that has a faulty local RAM is useless. Furthermore, a fault-free RAM cannot be used if the corresponding node router is faulty View full abstract»

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  • A large-area integrated multiprocessor system for video applications

    Page(s): 6 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB)  

    This 16.89 cm2 multiprocessor system performs coding of high-resolution video streams in real time. Redundancy and self-reconfiguration techniques ensure high reliability with a suitable yield. We used our own built-in self-test approach, which allows parallel testing of the processor cores View full abstract»

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  • Improving SoC design quality through a reproducible design flow

    Page(s): 76 - 83
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    The author examines the dynamics of system-on-a-chip design and addresses the fundamental question of whether there is a reproducible process for achieving the right design at the right time View full abstract»

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  • Jitter testing for gigabit serial communication transceivers

    Page(s): 66 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (601 KB)  

    Proper testing of transceivers requires the ability not only to measure generated jitter but also to inject in-band as well as out-of-band jitter for an appropriate receiver tolerance test. The article introduces a low-cost method to extend jitter testing to conventional external loop-back testing (looping the transmitted signal back to its own receiver) or golden device testing (using a known good device to test its link partner). The technique introduced is independent of test platforms View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty