IEEE Transactions on Computers

Issue 1 • Jan. 2002

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Displaying Results 1 - 9 of 9
  • Editor's Note

    Publication Year: 2002, Page(s):1 - 2
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    Freely Available from IEEE
  • Comment on "Generic universal switch blocks"

    Publication Year: 2002, Page(s):93 - 95
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (104 KB) | HTML iconHTML

    M. Shyu et al. (2000) defined the well-structured symmetric switch block M/sub N,W/ and showed that M/sub N,W/ is universal for any pair of positive integers N and W. However, we find that this result is partially correct. In this paper, we show that, when N/spl ges/7, M/sub N,W/ is not universal for odd Ws (/spl ges/3) and it is universal for any even W. View full abstract»

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  • High-speed and reduced-area modular adder structures for RNS

    Publication Year: 2002, Page(s):84 - 89
    Cited by:  Papers (57)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (130 KB) | HTML iconHTML

    A modular adder is a very instrumental arithmetic component in implementing online residue-based computations for many digital signal processing applications. It is also a basic component in realizing modular multipliers and residue to binary converters. Thus, the design of a high-speed and reduced-area modular adder is an important issue. In this paper, we introduce a new modular adder design. It... View full abstract»

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  • Constructing one-to-many disjoint paths in folded hypercubes

    Publication Year: 2002, Page(s):33 - 45
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (418 KB) | HTML iconHTML

    Routing functions have been shown effective in deriving disjoint paths in the hypercube. In this paper, using a minimal routing function, k+1 disjoint paths from one node to another k+1 distinct nodes are constructed in a k-dimensional folded hypercube whose maximal length is not greater than the diameter plus one, which is minimum in the worst case. For the general case, the maximal length is nea... View full abstract»

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  • A new hardware architecture for operations in GF(2n)

    Publication Year: 2002, Page(s):90 - 92
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (109 KB) | HTML iconHTML

    The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconventional basis and present a new bit-parallel multiplier which is as efficient as the modified Masse... View full abstract»

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  • A fast and efficient processor allocation scheme for mesh-connected multicomputers

    Publication Year: 2002, Page(s):46 - 60
    Cited by:  Papers (47)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (826 KB) | HTML iconHTML

    Efficient processor allocation is crucial for obtaining high performance in space-shared parallel computers. A good processor allocation algorithm should find available processors for incoming jobs, if they exist, with minimum overhead. In this paper, we propose such a fast and efficient processor allocation scheme for mesh-connected multicomputers. By using simple coordinate calculation and spati... View full abstract»

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  • Coverage estimation using statistics of the extremes for when testing reveals no failures

    Publication Year: 2002, Page(s):3 - 12
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (224 KB) | HTML iconHTML

    The existing classes of fault coverage models require an a priori distribution for collected data in their analysis. Using these models, analyses can be performed using various assumed distributions. The assumed distributions may not accurately reflect the behavior of the collected data and, as a result, the coverage values predicted by the models may be inaccurate, especially if testing yields li... View full abstract»

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  • Efficient and user-friendly verification

    Publication Year: 2002, Page(s):61 - 83
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (627 KB) | HTML iconHTML

    A compositional verification method from a high-level resource-management standpoint is presented for dense-time concurrent systems and implemented in the tool of SGM (State-Graph Manipulators) with graphical user interface. SGM packages sophisticated verification technology into state-graph manipulators and provides a user interface which views state-graphs as basic data-objects. Hence, users do ... View full abstract»

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  • On the quality of service of failure detectors

    Publication Year: 2002, Page(s):13 - 32
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (321 KB) | HTML iconHTML

    We study the quality of service (QoS) of failure detectors. By QoS, we mean a specification that quantifies: (1) how fast the failure detector detects actual failures and (2) how well it avoids false detections. We first propose a set of QoS metrics to specify failure detectors for systems with probabilistic behaviors, i.e., for systems where message delays and message losses follow some probabili... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org