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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 4 • Date Oct. 2001

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Displaying Results 1 - 19 of 19
  • Editorial

    Publication Year: 2001 , Page(s): 237 - 238
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  • Abstracts

    Publication Year: 2001 , Page(s): 239 - 242
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  • Author index

    Publication Year: 2001 , Page(s): 359 - 361
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  • Subject index

    Publication Year: 2001 , Page(s): 361 - 366
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  • Neural network modeling with confidence bounds: a case study on the solder paste deposition process

    Publication Year: 2001 , Page(s): 323 - 332
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    The formation of reliable solder joints in electronic assemblies is a critical issue in surface mount manufacturing. Stringent control is placed on the solder paste deposition process to minimize soldering defects and achieve high assembly yield. Time series process modeling of the solder paste quality characteristics using neural networks (NN) is a promising approach that complements traditional control charting schemes deployed on-line. We present the study of building a multilayer feedforward neural network for monitoring the solder paste deposition process performance. Modeling via neural networks provides not only useful insights in the process dynamics, it also allows forecasts of future process behavior to be made. Data measurements collected on ball grid array (BGA) and quad flat pack (QFP) packages are used to illustrate the NN technique and the forecast accuracies of the models are summarized. Furthermore, in order to quantify the errors associated with the forecasted point estimates, asymptotically valid prediction intervals are computed using nonlinear regression. Simulation results showed that the prediction intervals constructed give reasonably satisfactory coverage percentages as compared to the nominal confidence levels. Process control using NN with confidence bounds provides more quality information on the performance of the deposition process for better decision making and continuous improvement View full abstract»

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  • Integrated capacitors for conductive lithographic film circuits

    Publication Year: 2001 , Page(s): 333 - 338
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (97 KB) |  | HTML iconHTML  

    This paper reports on fabrication of low-value embedded capacitors in conductive lithographic film (CLF) circuit boards. The CLF process is a low-cost and high speed manufacturing technique for flexible circuits and systems. We report on the construction and electrical characteristics of CLF capacitor structures printed onto flexible substrates. These components comprise a single polyester dielectric layer, which separates the printed electrode films. Multilayer circuit boards with printed components and interconnect can be fabricated using this technique View full abstract»

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  • Application assessment of high throughput flip chip assembly for a high lead-eutectic solder cap interconnect system using no-flow underfill materials

    Publication Year: 2001 , Page(s): 307 - 312
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (207 KB) |  | HTML iconHTML  

    Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance View full abstract»

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  • The current status of lead-free solder alloys

    Publication Year: 2001 , Page(s): 244 - 248
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    The issue of lead-free soldering has gripped the electronics assembly industry as of late. What was once something that appeared to be too far away to worry about now has become a pressing reality. In order to avoid confusion, panic, and a misunderstanding of how the issue of lead-free soldering will affect the industry and individuals, it is necessary for all suppliers and assemblers to become educated in this matter. There currently exist several lead-free alloys deemed "acceptable" for various applications. However, it is important to note that many differences occur from alloy to alloy, and much research and background information is required before the successful implementation of a lead-free solder. This paper shall provide a comparison of the tin-silver, tin-copper, and tin-silver-copper alloys with each other and the tin-lead alloy, and well as process advice for the implementation of these solders and an overview of where the industry stands on the issue today. Highlighted in this is comparative test data of the aforementioned alloys, along with a discussion of other "alternative" alloys View full abstract»

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  • Characterization of the melting and wetting of Sn-Ag-X solders

    Publication Year: 2001 , Page(s): 255 - 260
    Cited by:  Papers (8)
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    There is tremendous interest at present with Pb-free solder assembly in the surface mount assembly industry in response to recent Japanese and European initiatives and proposed governmental restrictions regarding Pb usage and disposal. Many different solder alloys have been proposed as potential Pb-free solder replacements and the most promising of these fall into the general alloy families of tin-silver (Sn-Ag), tin-silver-copper (Sn-Ag-Cu) and tin-silver-bismuth (Sn-Ag-Bi). Published melting point data on some of these alloys indicates that they should be capable of reduced reflow temperatures relative to the commonly available Sn-3.5Ag alloy, which melts at 221°C. Differential scanning calorimetry (DSC) and reflow visualization was used to characterize the melting and wetting of the Pb-free alloys and generate the practical reflow temperature requirements. This was compared to the DSC data to gain insight on the meaning of the DSC melting data for surface mount applications. The results show that, in general, the wetting performance of the Sn-Ag-Bi alloys are more similar to Sn-Ag and Sn-Ag-Cu than would be predicted by the major onset melting temperature data as measured by the DSC View full abstract»

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  • Flip chip die attach development for multichip mechatronics power packages

    Publication Year: 2001 , Page(s): 300 - 306
    Cited by:  Papers (4)
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    New package innovations are needed to address the next generation system requirements of the automotive market. Enhanced system functionality from semiconductor components and overall cost reduction demands drive multichip package solutions. The use of semiconductor devices to switch, control and monitor high current loads will integrate logic and power devices on a common substrate with requirements for effective power dissipation, current carrying capability and fine width conductor features for the control device and interconnections. To achieve these goals Motorola's Advanced Interconnection Systems Laboratory, Munich, has developed a new package concept, a multichip mechatronics power package, utilizing flip chip die attach technology and electroplated eutectic SnPb solder bumps. With the goal to deliver an advanced package platform to cover different power levels in the system architecture,the several substrate technologies were evaluated View full abstract»

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  • Flip chip interconnect systems using copper wire stud bump and lead free solder

    Publication Year: 2001 , Page(s): 261 - 268
    Cited by:  Papers (9)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly View full abstract»

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  • Part assessment guidelines and criteria for parts selection and management

    Publication Year: 2001 , Page(s): 339 - 350
    Cited by:  Papers (5)
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    Parts selection and management is a process designed to evaluate the risks inherent in the use of an electronic part (e.g., a resistor, diode, or integrated circuit), and then facilitate informed decisions regarding its selection and future management activities. One step in the process is part assessment, which evaluates a part's quality and integrity. This involves comparing data acquired for the part with predetermined criteria to determine if the part will function acceptably in an equipment manufacturer's product. This paper presents the part assessment process, along with the criteria developed for assessment. The process and criteria were developed by analyzing industry standards and existing company methods, consulting with industry and academia experts, and conducting a case study of 113 electronic parts. The results of the case study are also provided View full abstract»

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  • Characteristics extraction of Pb free solder fillet profile for external feature inspection

    Publication Year: 2001 , Page(s): 313 - 322
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (535 KB) |  | HTML iconHTML  

    First, the light intensity (luminance) distributions reflected from quad flat package (QFP) gull wing lead solder fillets were calculated by a simple geometrical model, using a modified diffusion equation. The dependence of the microscope angle θ (= incident angle of light) on the highlight distribution from specular surfaces was obtained. Luminance distributions from top to toe fillets were experimentally observed, using Sn-Pb eutectic solder and two kinds of Pb-free solder (Sn-Ag-Cu and Sn-Zn-Bi systems) and the characteristics were compared with the simulation results. As the Sn-Pb solder fillet has a specular (or smooth) surface, it is not so difficult to identify the profiles of Sn-Pb fillets by changing θ. On the other hand, the luminance distributions for Pb-free solder were strongly affected by the surface roughness. However, it is not impossible to extract the characteristics of the fillet profile if wetting properties of Pb-free solder are taken into consideration. It was found for Pb-free solder that the fillet formation characteristics extraction becomes easy if elements of Bi and In are doped because the wetting properties were improved. In addition, some problems with characteristics extraction of fillet formation for Pb free solder are discussed from the viewpoint of an external feature inspection system View full abstract»

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  • Underfilling fine pitch BGAs

    Publication Year: 2001 , Page(s): 293 - 299
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (190 KB) |  | HTML iconHTML  

    Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty passing mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165°C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results View full abstract»

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  • Understanding the process window for printing lead-free solder pastes

    Publication Year: 2001 , Page(s): 249 - 254
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (341 KB) |  | HTML iconHTML  

    Solder paste is primarily used as a bonding medium for surface mount assemblies (SMA) in the electronics industry, and is typically deposited using the stencil printing process. Stencil printing is a very important and critical stage in the reflow soldering of surface mount devices, and a high proportion of all SMA defects are related to this process. This is likely to continue with the drive toward the introduction of lead-free solder pastes. Work is continuing on the metallurgical properties of these lead-free solders, including solder joint strength and material compatibility. However, the initial challenge for the new Pb-free formulations is in achieving repeatable solder deposit from print to print and from pad to pad. To meet this challenge, new flux formulations are being developed. For a smooth transition to Pb-free soldering formulations, a proper understanding of the solder paste printing performance is necessary. The key parameters that affect solder paste printing have been identified and are the subject of numerous studies. In lead-free solder paste, the replacement of lead with other elements (including Bi, Cu) changes the density of this dense suspension. In this paper, we investigate the effects of printer parameters, i.e. squeegee speed and pressure (defined as the process window) on the printing performance of a variety of lead-free solder pastes. A three-level design of experiment on these factors was used. Comparisons are presented with lead-rich solder pastes. The metal content of the lead-free solders had a significant effect on the process window View full abstract»

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  • Comparison of electroplated eutectic Bi/Sn and Pb/Sn solder bumps on various UBM systems

    Publication Year: 2001 , Page(s): 269 - 274
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    The effect of a reflow process and under bump metallurgy (UBM) systems on the growth of intermetallic compounds (IMC) of the 57Bi/43Sn and 37Pb/63Sn solder bump/UBM interfaces was investigated. The selected UBM systems were sputtered Al/Ti/Cu, sputtered Al/NiV/Cu, Al/electroless Ni/immersion Au, and Al/Ti/electroless Cu. An alloy electroplating method was used for the solder bumping process. The microstructure and composition of intermetallic compound (IMC) phases and their morphologies were examined using scanning electron microscopy and X-ray diffraction. The Cu6Sn5 η'-phase IMC appeared on all Cu containing UBM cases with Pb/Sn and Bi/Sn solders and the Cu 3Sn ε-phase was detected only with Pb/Sn solder bumps. The Ni3Sn4 IMC was found to be the main IMC phase between Ni and solder. The Ni3Sn secondary IMC was also detected on the electroless Ni UBM with PbSn solder after ten times reflow. Through the bump shear test, Al/NiV/Cu, Al/elNi/Au, and Al/Ti/elCu UBMs showed good stability with Bi/Sn and Pb/Sn solder in terms of metallurgical aspects View full abstract»

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  • Manufacturer assessment procedure and criteria for parts selection and management

    Publication Year: 2001 , Page(s): 351 - 358
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB) |  | HTML iconHTML  

    Parts selection and management is a process designed to evaluate the risks inherent in the use of an electronic part (e.g., a resistor, diode, or integrated circuit), and then facilitate informed decisions regarding its selection and future management activities. One step in the process is the assessment of the part manufacturer, which involves comparing data acquired for the manufacturer with predetermined criteria to determine if the manufacturer's policies and procedures are consistent with producing quality and reliable parts. This paper presents the manufacturer assessment process, along with the criteria developed for assessment. The process and criteria were developed by analyzing industry standards and existing company methods, consulting with industry and academia experts, and conducting a case study of 36 electronic part manufacturers. The results of the case study are also provided View full abstract»

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  • Eutectic Sn-Ag solder bump process for ULSI flip chip technology

    Publication Year: 2001 , Page(s): 275 - 281
    Cited by:  Papers (13)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than ±0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260°C in N2 ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150°C for 1000 h in N2 ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs View full abstract»

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  • Lead-free solder flip chip-on-laminate assembly and reliability

    Publication Year: 2001 , Page(s): 282 - 292
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (354 KB) |  | HTML iconHTML  

    This paper examines the assembly process for flip chip die with SnAgCu solder bumps and the results of liquid-to-liquid thermal shock testing. The SnAgCu alloy required a thicker dip layer of flux to achieve good wetting compared to the SnPb eutectic alloy. A liquid spray flux yielded more consistent solder wetting with the SnAgCu alloy. With both fluxes, a nitrogen reflow atmosphere was necessary with the SnAgCu alloy. A peak reflow temperature of 246°C was used for the assembly of the SnAgCu thermal shock test vehicles. A lower peak temperature of 235°C did not yield sufficient solder wetting. Liquid-to-liquid thermal shock testing was performed from -40°C to +125°C. The SnPb alloy performed slightly better than the SnAgCu and the dip flux was better that the spray flux. The degree of delamination with the SnAgCu alloy was significantly higher than with the SnPb alloy. Cracks in the underfill between adjacent solder balls were observed. The SnPb alloy extruded into these cracks more readily than the SnAgCu and created electrical shorts View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University