By Topic

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 6 • Date Dec. 2001

Filter Results

Displaying Results 1 - 25 of 27
  • Guest editorial: system level design

    Publication Year: 2001 , Page(s): 741 - 742
    Save to Project icon | Request Permissions | PDF file iconPDF (16 KB)  
    Freely Available from IEEE
  • Synthesis of hardware models in C with pointers and complex data structures

    Publication Year: 2001 , Page(s): 743 - 756
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB)  

    One of the greatest challenges in a C/C++-based design methodology is efficiently mapping C/C++ models into hardware. Many networking and multimedia applications implemented in hardware or mixed hardware/software systems now use complex data structures stored in multiple memories, so many C/C++ features that were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation and pointers for managing data. We present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. Our solution, which fits current memory management methodologies, instantiates an application-specific hardware memory allocator coupled with a memory architecture. Our work also supports the resolution of pointers without restriction on the data structures. We present an implementation based on the SUIF framework along with case studies such as the realization of a video filter and an ATM segmentation engine. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Quantifying and enhancing power awareness of VLSI systems

    Publication Year: 2001 , Page(s): 757 - 772
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB) |  | HTML iconHTML  

    An increasingly important figure-of-merit of a VLSI system is "power awareness," which is its ability to scale power consumption in response to changing operating conditions. These changes might be brought about by the time-varying nature of inputs, desired output quality, or just environmental conditions. Regardless of whether they were engineered for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are "more" power aware than others. Equivalently, we should be able to re-engineer systems to increase their power awareness. In this paper, we attempt to quantitatively define power awareness and how such awareness can be enhanced using a systematic technique. We illustrate this technique by applying it to VLSI systems at several levels of the system hierarchy - multipliers, register files, digital filters, dynamic voltage-scaled processors, and data-gathering wireless networks. It is seen that, as a result, the power awareness of these preceding systems can be significantly enhanced leading to increases in battery lifetimes in the range of 60-200%. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Path clustering in software timing analysis

    Publication Year: 2001 , Page(s): 773 - 782
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    Verification of program running time is essential in system design with real-time constraints. Simulation with incomplete test patterns or simple instruction counting are not appropriate for complex architectures. Software running times of embedded systems are process state and input data dependent. Formal analysis of such dependencies leads to software running time intervals rather than single values. These intervals depend on program properties, execution paths, and states of processes, as well as on the target architecture. An approach to analysis of process behavior using running time intervals is presented. It improves our previous work by exploiting program segments with single paths and by taking the execution context into account. The example of an asynchronous transfer mode (ATM) cell handler demonstrates significant improvements in analysis precision. Experimental results show the superiority of the presented approach over well-established approaches. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Polynomial circuit models for component matching in high-level synthesis

    Publication Year: 2001 , Page(s): 783 - 800
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    Design reuse requires engineers to determine whether or not an existing block implements desired functionality. If a common high-level circuit model is used to represent components that are described at multiple levels of abstraction, comparisons between circuit specifications and a library of potential implementations can be performed accurately and quickly. A mechanism is presented for compactly specifying circuit functionality as polynomials at the word level. Polynomials can be used to represent circuits that are described at the bit level or arithmetically. Furthermore, in representing components as polynomials, differences in precision between potential implementations can be detected and quantified. We present a mechanism for constructing polynomial models for combinational and sequential circuits. Furthermore, we derive a means of approximating the functionality of nonpolynomial functions and determining a bound on the error of this approximation. These methods have been implemented in the POLYSYS synthesis tool and used to synthesize a JPEG encode block and infinite impulse response filter from a library of complex elements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Influence of compiler optimizations on system power

    Publication Year: 2001 , Page(s): 801 - 804
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (106 KB) |  | HTML iconHTML  

    Optimizing for energy constraints is of critical importance due to the proliferation of battery-operated embedded devices. Thus, it is important to explore both hardware and software solutions for optimizing energy. The focus of high-level compiler optimizations has traditionally been on improving performance. In this paper, we present an experimental evaluation of several state-of-the-art high-level compiler optimizations on energy consumption, considering both the processor core (datapath) and memory system. This is in contrast to many of the previous works that have considered them in isolation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device

    Publication Year: 2001 , Page(s): 805 - 812
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (107 KB) |  | HTML iconHTML  

    We introduce the application of current techniques for hardware synthesis of combinational logic blocks to large-scale software partitions for eventual implementation of these partitions in a novel memory device called "Co-RAM." The novelty of our approach is based upon the observation that a wide variety of largescale software functionality can be considered "stateless" by conventional hardware synthesis tools and so may be realized as combinational logic. By limiting the functions placed in memory to combinational functions, we eliminate conventional synchronization overhead associated with coprocessors. A significant aspect of Co-RAM is that it is a system design concept that inherently merges hardware and software design styles at the system level, impacting programming styles, system build approaches, and the programmer's view of the underlying machine. A direct consequence of viewing the functionality as combinational is that the system state is not partitioned with the tasks. By Considering Co-RAM functionality to be stateless with respect to system state, Co-RAM functionality is inlined around the advancement of effectively unpartitioned system state. The rules for procedural combinational logic synthesis are shown to apply to a wide variety of software partitions. Results of our investigation project speedups of 8/spl times/ to 1000/spl times/ for a range of algorithms of varying problem size and for projected devices ranging from conventional field programmable gate arrays (FPGAs) to highly specific combinational logic devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Soft digital signal processing

    Publication Year: 2001 , Page(s): 813 - 823
    Cited by:  Papers (82)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delay imbalance" are employed. A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60-81% reduction in energy dissipation for filter bandwidths up to 0.5 /spl pi/ (where 2 /spl pi/ corresponds to the sampling frequency f/sub s/) over that achieved via conventional architecture and voltage scaling, with a maximum of 0.5-dB degradation in the output signal-to-noise ratio (SNR/sub o/). It is also shown that the proposed algorithmic noise-tolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • TAO: regular expression-based register-transfer level testability analysis and optimization

    Publication Year: 2001 , Page(s): 824 - 832
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB) |  | HTML iconHTML  

    In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimating probabilistic timing performance for real-time embedded systems

    Publication Year: 2001 , Page(s): 833 - 844
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    In system-level design of real-time embedded systems, being able to capture the interactions among the tasks with respect to timing constraints and determine the overall system timing performance is a major challenge. Most previous works in the area are either based on a fixed execution time model or are only concerned with the probabilistic timing behavior of each individual task. The few papers that deal with overall system probabilistic behavior have used improper assumptions. In this paper, given that the execution time of each task is a discrete random variable, a novel concept of state is introduced based on a new metric that is derived that measures the probability of a task set being able to be scheduled. Several approaches to evaluating the metric are also presented. Applying this metric in the system-level design exploration process, one can readily compare the probabilistic timing performance of alternative designs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic generation and compaction of March tests for memory arrays

    Publication Year: 2001 , Page(s): 845 - 857
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A framework for reconfigurable computing: task scheduling and context management

    Publication Year: 2001 , Page(s): 858 - 873
    Cited by:  Papers (29)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient exponentiation using weakly dual basis

    Publication Year: 2001 , Page(s): 874 - 879
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB) |  | HTML iconHTML  

    A new architecture for finite field exponentiation using weakly dual bases is presented. An extended bidirectional linear feedback shift register is designed to multiply an arbitrary field element with certain essential multiplicands in weakly dual basis (WDB). Each of these multiplications is done in one single clock cycle. It is shown that a bit parallel implementation of the WDB fourth power has complexities comparable to those of polynomial basis fourth power. The proposed structure can effectively speed up the computation of exponentiation and is expected to reduce the power consumption compared to the conventional square and multiply scheme. Compared to the structure for polynomial basis exponentiation, the new structure is thus advantageous in a system where the WDB is already available. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parameterized RTL power models for soft macros

    Publication Year: 2001 , Page(s): 880 - 887
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (145 KB) |  | HTML iconHTML  

    We propose a new power macromodel for usage in the context of register-transfer level (RTL) power estimation. The model is suitable for reconfigurable, synthesizable, soft macros because it is parameterized with respect to the input data size (i.e., bit width) and can also be automatically scaled with respect to different technology libraries and/or synthesis options. The power model is precharacterized once and for all for each soft macro and then adapted to each specific instance by means of a single additional experiment to be performed by the end user. No intellectual-property disclosure is required for model scaling. The proposed model is derived from empirical analysis of the sensitivity of power consumption on input statistics, input data size, and technology. The experiments prove that with limited approximation, it is possible to decouple the effects on power of these three factors. The proposed solution is innovative since no previous macromodel supports automatic technology scaling and yields average estimation errors around 10%. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Statistical clock skew modeling with data delay variations

    Publication Year: 2001 , Page(s): 888 - 898
    Cited by:  Papers (29)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (334 KB)  

    Accurate clock skew budgets are important for microprocessor designers to avoid hold-time failures and to properly allocate resources when optimizing global and local paths. Many published clock skew budgets neglect voltage jitter and process variation, which are becoming dominant factors in otherwise balanced H-trees. However, worst-case process variation assumptions are severely pessimistic. This paper describes the major sources of clock skew in a microprocessor using a modified H-tree and applies the model to a second-generation Itanium-M processor family microprocessor currently under design. Monte Carlo simulation is used to develop statistical clock skew budgets for setup and hold time constraints in a four-level skew hierarchy. Voltage jitter through the phase locked loop (PLL) and clock buffers accounts for the majority of skew budgets. We show that taking into account the number of nearly critical paths between clocked elements at each level of the skew hierarchy and variations in the data delays of these paths reduces the difference between global and local skew budgets by more than a factor of two. Another insight is that data path delay variability limits the potential cycle-time benefits of active deskew circuits because the paths with the worst skew are unlikely to also be the paths with the longest data delays. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

    Publication Year: 2001 , Page(s): 899 - 912
    Cited by:  Papers (26)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (279 KB)  

    A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A differential equation for placement analysis

    Publication Year: 2001 , Page(s): 913 - 921
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (185 KB) |  | HTML iconHTML  

    A first-order differential equation for placement analysis is derived by considering the competing processes that generate and terminate wires crossing a circuit partition. The solution of this equation provides an estimate for the number of wires needed by a circuit partition for external communication and corresponds to the information normally associated with Rent's rule. The rate model is shown to account not only for the simple power-law form of Rent's rule for small partition sizes but also for deviations from power-law behavior observed for larger partition sizes. The accuracy of the model is validated by comparing solutions of the differential equation with experimental data extracted from a variety of netlists. The netlists, ranging from 10000 to 68000 cells, were optimized using a commercial placement tool. The accurate modeling of terminal-cell data results in a more robust predictive model for the distribution of wire lengths. This improved model accurately captures the change in the distribution of wires as the level of circuit placement optimization ranges from random to highly optimized placement. In addition, the new model provides an explanation for the experimentally observed inflection point and local maximum in the wire length distribution of some netlists. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of three-dimensional architectures on interconnects in gigascale integration

    Publication Year: 2001 , Page(s): 922 - 928
    Cited by:  Papers (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (157 KB) |  | HTML iconHTML  

    An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9/spl times/ increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Buffer block planning for interconnect planning and prediction

    Publication Year: 2001 , Page(s): 929 - 937
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    This paper studies buffer block planning (BBP) for interconnect planning and prediction in deep submicron designs. We first introduce the concept of a feasible region for buffer insertion, and derive its closed-form formula. We observe that the feasible region for a buffer is quite large in general even under fairly tight delay constraint. Therefore, it gives a lot of flexibility to plan for buffer locations. We then develop an effective BBP algorithm to perform buffer clustering such that design objectives such as overall chip area and the number of buffer blocks can be minimized. Effective BBP can plan and predict system-level interconnect by construction, so that accurate interconnect information can be used in early design stages to ensure design closure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A stochastic model for the interconnection topology of digital circuits

    Publication Year: 2001 , Page(s): 938 - 942
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (90 KB) |  | HTML iconHTML  

    Rent's rule has been successfully applied to a priori estimation of wire length distributions. However, this approach is very restrictive: the circuits are assumed to be homogeneous. In this paper, recursive clustering is described as a more advanced model for the partitioning behavior of digital circuits. It is applied to predict the variance of the terminal count distribution. First, the impact of the block degree distribution is analyzed with a simple model. A more refined model incorporates the effect of stochastic self similarity. Finally, the model is further extended to describe the effects of heterogeneity. This model is a promising candidate for more accurate a priori estimation tools. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Prelayout estimation of individual wire lengths

    Publication Year: 2001 , Page(s): 943 - 958
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (351 KB)  

    We present a novel technique for estimating individual wire lengths in a given standard-cell-based design during the technology mapping phase of logic synthesis. The proposed method is based on creating a black box model of the place and route tool as a function of a number of parameters, which are all available before layout. The place and route tool is characterized, only once, by applying it to a set of typical designs in a certain technology. We also propose a net bounding box estimation technique based on the layout style and net neighborhood analysis. We show that there is inherent variability in wire lengths obtained using commercially available place and route tools-wire length estimation error cannot be any smaller than a lower limit due to this variability. The proposed model works well within these variability limitations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multilevel reverse most-significant carry computation

    Publication Year: 2001 , Page(s): 959 - 962
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (83 KB) |  | HTML iconHTML  

    A fast calculation of the most-significant carry in an addition is required in several applications. It has been proposed to calculate this carry by detecting the most-significant carry chain and collecting the carry after this chain. The detection can be implemented by a prefix tree of AND gates and the collecting by a multi-input OR. We propose a multilevel implementation, which allows the overlap of successive levels, thereby reducing the overall delay. For 64-bit operands we estimate a delay reduction of about 15% with respect to the traditional carry-lookahead-based method, with a similar hardware complexity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Exploiting the on-chip inductance in high-speed clock distribution networks

    Publication Year: 2001 , Page(s): 963 - 973
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (163 KB) |  | HTML iconHTML  

    On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses

    Publication Year: 2001 , Page(s): 974 - 982
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    This paper presents a methodology for designing system-on-chip (SOC) interconnection architectures providing a high level of protection from crosstalk effects. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and, thus, designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cell-based layout techniques supporting gate-level voltage scaling for low power

    Publication Year: 2001 , Page(s): 983 - 986
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (146 KB) |  | HTML iconHTML  

    Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this correspondence, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then, we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu