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IEEE Design & Test of Computers

Issue 4 • Aug. 1990

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Displaying Results 1 - 7 of 7
  • Verifying a multiprocessor cache controller using random test generation

    Publication Year: 1990, Page(s):13 - 25
    Cited by:  Papers (26)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1062 KB)

    The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop... View full abstract»

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  • Embedded totally self-checking checkers: a practical design

    Publication Year: 1990, Page(s):5 - 12
    Cited by:  Papers (28)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    In a totally self-checking (TSC) design, the circuit detects errors by monitoring redundantly coded data/control paths through a TSC checker. A problem arises when not all these code words are on the monitored lines during normal operation. A method of designing checkers that solves this difficulty is proposed. The method uses TSC checkers based on flip-flops instead of using the mostly combinatio... View full abstract»

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  • Improved test generation for high-activity circuits

    Publication Year: 1990, Page(s):26 - 31
    Cited by:  Papers (3)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB)

    An implementation of a test-pattern generator based on the Podem (path-oriented decision-making) algorithm is proposed. Podem uses a depth-first search from the fault location to assign primary input values. The result of these assignments at internal nodes is then determined by logic simulation (implication). Podem must compute primary input combinations that both excite the fault and propagate i... View full abstract»

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  • Fault sampling revisited

    Publication Year: 1990, Page(s):32 - 35
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (201 KB)

    In the text, Test Generation for VLSI Chips (see IEEE Computer Society Press, 1988), V. Agrawal and S. Seth gave a formula for estimating fault coverage from the coverage analysis of randomly sampled faults that contains an error. A corrected formula for the sample size required for a given error tolerance in the measurement of fault coverage is given. Easy-to-use guidelines for analyzing fault co... View full abstract»

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  • Are primitive polynomials always best in signature analysis?

    Publication Year: 1990, Page(s):36 - 38
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (207 KB)

    It is shown that in testing technique based on linear-feedback shift registers, the use of primitive polynomials in a signature-analysis register is not always better than using nonprimitive polynomials. The results show how some primitive polynomials may actually yield maximum aliasing errors. These results are based on the simulation of single stuck-at faults, but they also hold for certain mult... View full abstract»

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  • Dynamic statistical control of manufacturing test

    Publication Year: 1990, Page(s):39 - 51
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (982 KB)

    A method for controlling manufacturing tests in real time by statistically predicting test behavior is described. This statistical prediction is used to eliminate certain tests in sequential testing. Analytic methods for clustering tests for more efficient execution and an algorithm for predictive testing are presented. A relational database using structured-query-language system, called SQL/DB2 i... View full abstract»

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  • An efficient VLSI switch-box router

    Publication Year: 1990, Page(s):52 - 65
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (935 KB)

    A tool for switch-box routing that can route regions with cyclic constraints and with terminals on three or four sides is presented. A divide-and-conquer algorithm is used to explore the greedy channel routing idea, using techniques such as routing area partitioning, dynamic routing strategies, and sweeping concurrent bidirectional columns. The routing area is decomposed into three parts by two sp... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty