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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan 2002

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Displaying Results 1 - 25 of 35
  • Low-loss, high-voltage 6H-SiC epitaxial p-i-n diode

    Page(s): 150 - 154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1306 KB) |  | HTML iconHTML  

    The p-i-n diodes were fabricated using 31 μm thick n-- and p-type 6H-SiC epilayers grown by horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively. The diode exhibited a very high breakdown voltage of 4.2 kV with a low on-resistance of 4.6 mΩcm2. This on-resistance is lower (by a factor of five) than that of a Si p-i-n diode with a similar breakdown voltage. The leakage current density was substantially lower even at high temperatures. The fabricated SiC p-i-n diode showed fast switching with a turn-off time of 0.18 μs at 300 K. The carrier lifetime was estimated to be 0.64 μs at 300 K, and more than 5.20 μs at 500 K. Various characteristics of SiC p-i-n diodes which have an advantage of lower power dissipation owing to conductivity modulation were investigated. View full abstract»

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  • An experimental investigation on the nature of reverse current of silicon power pn-junctions

    Page(s): 155 - 163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1373 KB) |  | HTML iconHTML  

    At this time, little importance is given to the surface component of reverse leakage current of silicon pn-junctions although reliability issues reveal device blocking weakness when performing at high voltage and temperature. Junctions which have almost the same perimeter but different area have been realized and their reverse current has been measured at room temperature and high temperature both for standard recovery and fast recovery (gold-doped or electron irradiated) pn-junctions. It is shown that for standard recovery junctions the surface component of the reverse current is the primary component from room temperature up to above 150°C and has influence on reaching high permissible working voltages. For gold-doped or electron irradiated junctions, the bulk component is dominant at high junction temperature, but it is shown that a comparatively negligible surface component can impose lower reverse working voltages or lower junction operation temperature. The surface component may be a cause of limitation on the operation of power silicon diodes at high reverse voltage above 175-200°C junction temperature. View full abstract»

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  • Temperature behavior of visible and infrared electroluminescent devices fabricated on erbium-doped GaN

    Page(s): 48 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (127 KB) |  | HTML iconHTML  

    Visible and infrared (IR) rare-earth-activated light emission has been obtained from Er-doped GaN electroluminescent devices (ELD). The ELD consists of an in-situ Er-doped GaN layer grown on either a sapphire or silicon (Si) substrate. The temperature dependence of the light emission and the current conduction is reported. The EL spectrum shows two main visible peaks at 537 and 558 nm and a group of closely spaced IR peaks clustered around 1550 nm. The 558 nm visible transition is dominant below 250 K, whereas the 537 nm transition is dominant at higher temperature peaking at 300 K. Temperatures from 240-500 K have minimal effect on IR emission intensity. A simple model consisting of two back-to-back Schottky diodes explains the current-voltage dependence. The effect of Er doping and substrate type on carrier transport is investigated as a function of voltage and temperature. Specifically, there is evidence that an Er-related defect is responsible for carrier generation at temperatures above 300 K. The effect of bias polarity on spatial confinement of the light emission in different areas of the devices is discussed. The model indicates that both electric field intensity and current density are important in producing light emission. The model also accounts for the uniformity of the emission under the electrodes when considering the type of substrate used for GaN:Er device growth View full abstract»

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  • Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations

    Page(s): 112 - 119
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (163 KB) |  | HTML iconHTML  

    Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO2 and gate/SiO2 interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants View full abstract»

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  • Two-dimensional quantum effects in nanoscale MOSFETs

    Page(s): 25 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (130 KB) |  | HTML iconHTML  

    In this paper, a full two-dimensional (2-D) quantum mechanical (QM) device simulator for deep submicron MOSFETs is presented. The model couples a 2-D Schrodinger-Poisson solver with a semiclassical transport model. The validity of the proposed model is first tested against a QM model for transport, developed as a benchmark. Then, QM effects on nanoscale MOSFETs performance are quantitatively addressed and discussed. It is shown that QM effects strongly influence the device performance, namely subthreshold slope drain-induced barrier lowering and short-channel effects. These results show that full QM simulations will become a mandatory issue for nanoscale MOSFETs modeling and design View full abstract»

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  • A method to extract mobility degradation and total series resistance of fully-depleted SOI MOSFETs

    Page(s): 82 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    Free-carrier mobility degradation in the channel and drain/source series resistance are two important parameters limiting the performance of MOS devices. In this paper, we present a method to extract these parameters from the drain current versus gate voltage characteristics of fully-depleted (FD) SOI MOSFETs operating in the saturation region. This method is developed based on an integration function which reduces errors associated with the extraction procedure and on the DC characteristics of MOS devices having several different channel lengths. Simulation results and measured data of FD SOI MOSFETs are used to test and verify the method developed View full abstract»

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  • Clarification of floating-body effects on drive current and short channel effect in deep sub-0.25 μm partially depleted SOI MOSFETs

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (171 KB) |  | HTML iconHTML  

    We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (Vth) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller Vth-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current View full abstract»

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  • Novel phenomenon of avalanche breakdown saturation with negative resistance in a bipolar transistor

    Page(s): 120 - 124
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (90 KB) |  | HTML iconHTML  

    A breakdown saturation phenomenon of negative resistance has been observed in a bipolar transistor. The collector current becomes saturated and reaches a critical current (ICC) after avalanche breakdown. At this critical current, a negative resistance appears. ICC is determined by the thermal condition of the transistor, as obtained from pulse measurements and temperature dependence. For the multiplication factor (M), it is clear that there are two distinct regions: 1) low voltage (Region I) and 2) higher voltage (Region II). In Region I, the multiplication factor begins to increase with increasing applied voltage and is fixed almost constant for temperature, whereas in Region II, the multiplication factor decreases with increasing temperature. As a result, (∂M/∂V) T≃0 is realized at about 20 V and 124°C, corresponding to the saturation of avalanche breakdown View full abstract»

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  • Ultralow leakage characteristics of ultrathin gate oxides (~3 nm) prepared by anodization followed by high-temperature annealing

    Page(s): 179 - 181
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB) |  | HTML iconHTML  

    The leakage current of an anodic oxide (ANO) is two orders lower than that of a rapid thermal oxide (RTO) due to the negative oxide trapped charges near the metal-ANO interface. Moreover, the ANO's SILC characteristic is different from the RTO's, since the charges might redistribute under a high electrical stress View full abstract»

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  • Breakdown voltage and reverse recovery characteristics of free-standing GaN Schottky rectifiers

    Page(s): 32 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (113 KB) |  | HTML iconHTML  

    Schottky rectifiers with implanted p+ guard ring edge termination fabricated on free-standing GaN substrates show reverse breakdown voltages up to 160 V in vertical geometry devices. The specific on-state resistance was in the range 1.7-3.0 Ω·cm 2, while the turn-on voltage was ~1.8 V. The switching performance was analyzed using the reverse recovery current transient waveform, producing an approximate high-injection, level hole lifetime of ~15 ns. The bulk GaN rectifiers show significant improvement in forward current density and on-state resistance over previous heteroepitaxial devices View full abstract»

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  • Sub-50-nm physical gate length CMOS technology and beyond using steep halo

    Page(s): 89 - 95
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    Sub-50-nm CMOS devices are investigated using steep halo and shallow source/drain extensions. By using a high-ramp-rate spike annealing (HRR-SA) process and high-dose halo, 45-nm CMOS devices are fabricated with drive currents of 650 and 300 μA/μm for an off current of less than 10 nA/μm at 1.2 V with Toxinv =2.5 nm. For an off current less than 300 nA/μm, 33-nm pMOSFETs have a high drive current of 400 uA/μm. Short-channel effect and reverse short-channel effect are suppressed simultaneously by using the HRR-SA process to activate a source/drain extension (SDE) after forming a deep source/drain (S/D). This process sequence is defined as a reverse-order S/D (R-S/D) formation. By using this formation, 24-nm nMOSFETs are achieved with a high drive current of 800 μA/μm for an off current of less than 300 μA/μm at 1.2 V. This high drive current might be a result of a steep halo structure reducing the spreading resistance of source/drain extensions View full abstract»

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  • Preparation of thin-film transistors with chemical bath deposited CdSe and CdS thin films

    Page(s): 15 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB) |  | HTML iconHTML  

    The authors have fabricated the thin-film transistor (TFT) with CdSe and CdS semiconductor thin films, prepared by a low temperature chemical bath deposition (CBD) method, as an active layer. The ON-current values of the CdSe-TFTs and CdS-TFTs at a gate bias of 10 V and a source-drain voltage of 10 V are about 100 μA and 5 μA, respectively. The OFF-current values of the CdSe-TFTs and CdS-TFTs at the source-drain voltage of 10 V are less than 10 pA. The fabricated CdSe-TFTs exhibited a field effect mobility of 15 cm2/V-s, threshold voltage of 3.5 V, subthreshold slope of 0.5 V/dec., and ON/OFF current ratios exceed 107. A field effect mobility of I cm 2/V-s, a threshold voltage of 2.6 V, a subthreshold slope of 0.6 V/dec., and an ON/OFF current ratios exceed 106 were observed for CdS TFTs View full abstract»

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  • Stacked amorphous silicon color sensors

    Page(s): 170 - 176
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    Color sensors based on vertically integrated thin-film structures of amorphous silicon (a-Si:H) and its alloys were realized to overcome color moire or color aliasing effects. The complete color information of the color aliasing free sensors is detected at the same spatial position without the application of additional optical filters. The color separation is realized in the depth of the structure due to the strong wavelength dependent absorption of a-Si: H alloys in the visible range. The sensors consist of three stacked p-i-n diodes. The spectral sensitivity of the sensors can be controlled by the optical and electronic properties of the materials on one hand and the design of the devices on the other hand. In order to investigate the optical wave propagation within the device and to optimize the color separation we have developed an optical model, which takes the optical properties of the individual layers and the device design into account. The optical model has been combined with a colorimetric model, which facilitates the benchmarking of the color sensors and the reduction of the color error of the sensors. Finally, an improved device design is presented View full abstract»

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  • A simple, high performance TFSOI complementary BiCMOS technology for low power wireless applications

    Page(s): 200 - 202
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (102 KB)  

    The authors describe a simple, high performance thin-film silicon-on-insulator (TFSOI) complementary BiCMOS (C-BiCMOS) technology, which can be used in low power wireless communication applications. In this technology, a novel, high performance lateral BJT structure is implemented using a gate spacer to obtain a thin base width and a minimum base linkage to the external base for minimized base resistance. A lateral NPN transistor (with maximum oscillation frequency (fmax ) of 29 GHz, cut-off frequency (fT) of 8 GHz, current gain (hFE) of 78, and collect-emitter breakdown voltage with base open (BVCEO) of 5 V), a lateral PNP transistor (hFE of 51 and BVCEO of 4.5 V), and NMOS and PMOS transistors (0.5 μm channel length and 5 μm channel width, 0.5/-0.8 V threshold voltage) am fabricated. This technology provides very promising low power, low cost, and high performance solutions for RF mixed-signal system-on-a-chip (SoC) applications View full abstract»

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  • Novel SOI p-channel MOSFETs with higher strain in si channel using double SiGe heterostructures

    Page(s): 7 - 14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (211 KB) |  | HTML iconHTML  

    We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si0.82Ge0.18Si0.93Ge0.07 allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si0.9Ge0.1 structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively View full abstract»

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  • A scalable meander-line resistor model for silicon RFICs

    Page(s): 187 - 190
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (107 KB) |  | HTML iconHTML  

    A scalable lumped element model for meander-line resistors fabricated with the top-level metal of a silicon process that are suitable for radio frequency integrated circuit (RFIC) applications is presented. An optimization program is employed to extract the parameters of a physical equivalent circuit model. The simulated S-parameter data from the equivalent model shows very good agreement with the measured data View full abstract»

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  • Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

    Page(s): 37 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage VGoff is studied. It is shown that when VGoff is around the threshold voltage (pinchoff voltage) Vth, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when VGoff is much more negative than Vth View full abstract»

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  • Microwave performance and modeling of InAs/AlSb/GaSb resonant interband tunneling diodes

    Page(s): 19 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (110 KB) |  | HTML iconHTML  

    The microwave frequency performance of InAs/ AlSb/GaSb resonant interband tunneling diodes has been examined experimentally. A bias-dependent small-signal circuit model that matches the measured data well for the full range of measured frequencies (dc to 35 GHz) and the full range of device biases (0 to 0.5 V) has been obtained. To the author's knowledge, this is the first report of a microwave-frequency circuit model that is valid over the full range of device operating biases, including the negative differential resistance region. The bias dependence of the circuit elements contained within the model is examined, and is consistent with device operational principles View full abstract»

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  • The low frequency noise in reverse biased rectifier diodes

    Page(s): 184 - 187
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (137 KB) |  | HTML iconHTML  

    The low frequency noise in rectifier diodes in the breakdown regime is investigated as a function of the reverse current. A dynamic "competition" between impact ionization and microplasma switching explains the nonmonotonic, repetitive and correlated variations in the breakdown dynamic resistance (dV/dI) slope, the noise level, and the noise waveform View full abstract»

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  • Applications of blow-up theory to thyristor turn-on

    Page(s): 177 - 179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (101 KB)  

    An analysis of a symmetric double-gated thyristor is performed. By further imposing that the carrier transit times depend on the drift field, we arrive at a nonlinear partial differential equation. It describes the transverse behavior and admits blow-up-type solutions leading to current filamentation, i.e., a possible explanation for hot spots. The shortening of the bases during turn-on, associated with high drift fields expanding from the central junction toward the cathode junction is also predicted. These results could provide a simple interpretation for experimental data in GTOs published by other authors View full abstract»

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  • The PSD transfer function

    Page(s): 202 - 206
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    The authors describe the dynamic behavior of position sensitive detectors. Earlier work has described the PSD response to changes in light intensity. Here, we investigate the PSD response to a change of light spot position. We call the linear filter describing this response the PSD transfer function (PTF) View full abstract»

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  • MOSFET subthreshold compact modeling with effective gate overdrive

    Page(s): 196 - 199
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (150 KB)  

    In this work, a previously-proposed one-region MOSFET drain current (Id.) model is improved in the subthreshold modeling. The compact model is derived based on a first-principle drift-diffusion formulation with the correct drift and diffusion currents in strong inversion and subthreshold, respectively. The new model has only one fitting parameter for subthreshold slope and can ensure excellent continuity with smooth transition from subthreshold to strong-inversion regimes, including the moderate-inversion region of growing importance for low-voltage and low-power circuits View full abstract»

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  • Sub-100-nm vertical MOSFET with threshold voltage adjustment

    Page(s): 61 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (367 KB) |  | HTML iconHTML  

    Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical LDD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance View full abstract»

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  • Lateral thin-film Schottky (LTFS) rectifier on SOI: a device with higher than plane parallel breakdown voltage

    Page(s): 181 - 184
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB)  

    In this work, we report a lateral thin-film Schottky (LTFS) rectifier on a highly doped SOI epitaxial layer. Based on two-dimensional (2-D) numerical simulations, we demonstrate for the first time that, for an epitaxial doping of 1017 cm-3 , breakdown voltages as large as 60 V (about six times higher than the plane parallel breakdown voltage) can be achieved using the proposed structure with very low reverse leakage current. Further, the forward voltage drop of the proposed device is shown to be as low as 0.27 V even at a current density 100 A/cm2. The reasons for improved performance of the LTFS rectifier are analyzed and the effects of film thickness, Schottky barrier height, and the Si-SiO2 interface states on the device performance are also reported View full abstract»

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  • Accuracy of approximations in MOSFET charge models

    Page(s): 72 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (270 KB) |  | HTML iconHTML  

    This paper analyzes the results of common approximations made in MOSFET charge modeling. The basis for the comparison is a charge-sheet model that is valid in all regions of operation. We show that proper modeling of surface potential as a function of position along the channel is more important for capacitance coefficient modeling accuracy than partitioning of inversion charge between source and drain. In addition, we show that there is a numerical error in previous charge-sheet formulations, and provide a solution for this problem View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego