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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 2001

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Displaying Results 1 - 25 of 48
  • Investigation of temperature-dependent characteristics of an n/sup +/-InGaAs/n-GaAs composite doped channel HFET

    Page(s): 2677 - 2683
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    The temperature-dependent characteristics of an n+-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n+-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1 x 100 μm2 device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of Vth from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and wide operation regime. View full abstract»

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  • Author index

    Page(s): 2965 - 2984
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    Freely Available from IEEE
  • Subject index

    Page(s): 2984 - 3024
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    Freely Available from IEEE
  • DC pulse hot-carrier-stress effects on gate-induced drain leakage current in n-channel MOSFETs

    Page(s): 2746 - 2753
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    The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation View full abstract»

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  • Reexamination of the role of nitrogen in oxynitrides-fixed charge reduction in the p+-polysilicon gate MOS

    Page(s): 2777 - 2784
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    The problems associated with the use of p+-polysilicon gate MOS have been intensively investigated. Although the utilization of oxynitrides has been considered to be effective for the suppression of the threshold voltage (VT) deviation in the p+-polysilicon gate MOSFETs, the investigation revealed that the p+-polysilicon gate MOS exhibits significantly different properties when oxynitrides contain no nitrogen at the oxynitride/substrate interface (MOS interface) than it does with usual oxynitrides which contain nitrogen at the MOS interface. This discrepancy arises because, contrary to what is usually considered to be the case, boron diffused into the substrate is not the origin of the negative fixed charge generated in the p+-polysilicon gate MOS structures, which is one of the most important factors influencing VT in those structures. We have found fluorine in the p+-polysilicon gate MOS structures even when the polysilicon is doped using boron ion implantation. This is a consequence of the use of BF3 as a boron source. We propose a model in which fluorine is responsible for the negative fixed charge generation and nitrogen at the MOS interface prevents not only the boron penetration but also the negative fixed charge generation by suppressing the fluorine incorporation into the MOS interface View full abstract»

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  • Equivalent doping profile transformation: a semi-empirical, analytical method for predicting breakdown characteristics of an approximate single-diffused parallel-plane junction

    Page(s): 2763 - 2768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (107 KB) |  | HTML iconHTML  

    In this paper, a semi-empirical analytical method called the equivalent doping profile transformation method (EDPTM) has been proposed for the first time to predict the breakdown characteristics of an approximate single-diffused parallel-plane pn-junction that has a doping profile of the combination of a diffused side linear gradient constant and a constant substrate doping concentration, which considers the influence of the diffusion gradient level on the space charge region of the substrate side. Through the equivalent doping profile transformation, this approximate pn-junction turns into a double-sided asymmetric linear-graded junction (Jin et al., 1999). As a result, the breakdown voltage, critical peak electrical field, and the maximum depletion layer width can be carefully evaluated at different doping substrate concentration and gradient constant combinations. Compared with previous approximations such as abrupt and classical symmetrical linear-graded junctions, this method can give exact breakdown characteristics of a single-diffused pn-junction. The results are in excellent agreement with the numerical analysis, which proves the validity of this new method View full abstract»

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  • Isothermal DC and microwave characterizations of power RF silicon LDMOSFETs

    Page(s): 2785 - 2789
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    Presented in this paper are two new approaches for the acquisition of both isothermal DC current-voltage (I-V) characteristics and microwave S-parameters of power RF LDMOSFETs. In the first approach, a 3D tensor product B-spline representation is used to extract isothermal DC I-V characteristics from DC I-V characteristics measured at various substrate temperatures. The average device surface temperature is measured using an infrared sensor. A single effective thermal resistance is found to map the entire electrothermal profile of the device, justifying the isothermal DC I-V definition used. In the second approach, isothermal I-V and microwave data are directly measured with an efficient procedure that keeps the average device surface temperature constant. Excellent agreement is obtained between the numerical extraction and the direct measurement approach. Finally, the comparison of the transconductance extracted from the isothermal DC I-V and microwave data confirms the presence of a small low-frequency dispersion in LDMOSFETs not due to self-heating View full abstract»

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  • Improving the reliability and the insulation properties of gate oxide in the gate injection mode by using a new procedure of (100) Si surface and Si/SiO2 interface treatments

    Page(s): 2957 - 2959
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    A new two-step processing combination, for MOS devices improvement, is presented. It is composed of a pregate oxidation of (100) Si surface atomic scale flattening, which improves only the device breakdown reliability. Adding a postgate oxidation annealing step, using nitrogen monoxide (NO) gas mixture, reduces the degradation of the leakage current, which results from current stress application. A MOSFET with a gate oxide grown on an atomic scale flattened Si surface, exhibits a superior ID-VD characteristics, with respect to MOSFET fabricated on conventionally treated Si surface View full abstract»

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  • A novel 4.5-MW electron gun for a coaxial cavity gyrotron

    Page(s): 2938 - 2944
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB) |  | HTML iconHTML  

    A novel 4.5-MW (90 kV, 50 A) electron gun for a 165-GHz coaxial cavity gyrotron operated in the transverse electric mode TE31, 3.7 has been designed, fabricated, and operated in a gyrotron. The electrons are extracted toward the anode as in a conventional magnetron injection gun (MIG) and not toward the coaxial insert as in the previously used so-called inverse gun. The main advantage of this arrangement is the reduced overall radial size which becomes comparable to the size of a conventional gun with the same diameter of the emitter. The design and the technology of the electron gun fulfil the requirements for a high-power gyrotron operated at long pulses up to continuous wave. The coaxial insert is fully cooled and can be adjusted when the tube is completely assembled. The amplitude of mechanical vibrations has been measured to be less than 0.03 mm under operating conditions. This is sufficiently small for stable long-pulse operation. In operation at short pulses (ms) a microwave RF output power of 2.2 MW at 165 GHz has been obtained with a beam current of 84 A. The best operating conditions have been observed with an intermediate type of electron flow View full abstract»

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  • The influence of BF2 and F implants on the 1/f noise in SiGe HBTs with a self-aligned link base

    Page(s): 2808 - 2815
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    A study is made of 1/f noise in SiGe heterojunction bipolar transistors (HBTs) fabricated using selective growth (SEG) of the Si collector and nonselective growth (NSEG) of the SiGe base and Si emitter cap. The transistors incorporate a self-aligned link base formed by BF 2 implantation into the field oxide below the p+ polysilicon extrinsic base. The influence of this BF2 implant on the 1/f noise is compared with that of a F implant into the polysilicon emitter. Increased base current noise SIB and base current are seen in transistors annealed at 975°C, compared with transistors annealed at 950 or 900°C. At a constant collector current, both the BF2 and F implants reduce SIB, whereas at a constant base current, only the BF2 implant reduces SIB. This result indicates that the BF2 implant decreases the intensity of the base current noise source whereas the F implant decreases the base current. The proposed explanation for the increased 1/f noise is degradation of the surface oxide by viscous flow at 975°C under the influence of stress introduced during selective Si epitaxy. The influence of the BF2 implant on the noise is explained by the relief of the stress and hence the prevention of viscous oxide flow View full abstract»

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  • Analysis of bipolar junction transistors with a Gaussian base-dopant impurity-concentration profile

    Page(s): 2945 - 2947
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    A method for a quantitative charge-control analysis of bipolar base-junction transistors with a Gaussian dopant impurity-concentration profile is demonstrated. Analytical expressions for the base transit time are given for two different Gaussian impurity-concentration profiles with the peak concentration at the edge, and within the quasi-neutral base layer. It is also shown that approximating the Gaussian profile by a simple exponential profile results in only an insignificant error in the charge-control analysis View full abstract»

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  • Study of low-frequency charge pumping on thin stacked dielectrics

    Page(s): 2754 - 2762
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    The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO2 dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO2 dielectrics to thin stacked gate dielectrics are discussed View full abstract»

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  • Low frequency noise versus temperature spectroscopy of recently designed Ge JFETs

    Page(s): 2899 - 2905
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    During the investigation of cryogenic properties of recently developed Ge JFETs we have applied the technique known in literature as low frequency noise versus temperature spectroscopy (LFN versus T). Using this method we have determined the energy levels of traps associated to Lorentzian noise found in the 30 to 40 K temperature range. To perform this task we have developed a computer-controlled experimental setup able to set the temperature within ±5 mK in the range 4 to 300 K during a spectral noise measurement. An approach for the calculation of the uncertainties that affect the evaluation of traps parameter is presented View full abstract»

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  • Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

    Page(s): 2816 - 2822
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    Partial-trench-isolated (PTI) 0.18-μm SOI-CMOS technology has been established to realize the body-tied structure and eliminate floating-body effects. The body potential of PTI SOI MOSFETs is fixed through the silicon layer under the PTI oxide. It was revealed that the body-tied PTI structure provides immunity from kink effects and improves drive current as compared with floating transistors. The SOI inherent merits were investigated by delay-time measurement. Low junction capacitance, coupling effects and low back-gate-bias effects of PTI CMOS offer excellent speed performance. Stable function and body-coupling benefits are obtained with proper body engineering. The full-bit functions of a 4-Mbit SRAM were obtained with a reasonable yield. The yield of the SOI SRAM is almost the same as that of the bulk SRAM. An abnormal leakage current was not observed up to a supply voltage of 2.6 V corresponding to the stress voltage of the burn-in process. It was demonstrated that PTI technology possesses layout and process compatibility with bulk. It is concluded that the PTI technology can expand SOI applications in system-level large-scale integrations (LSIs) by cutting off the floating-SOI constraint View full abstract»

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  • A novel method to separately investigate program and erase degradation mechanisms in flash memory cells

    Page(s): 2947 - 2951
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    A novel method using a capacitor charging technique and a flash cell with access to the floating gate (FG) is developed to characterize the program and erase degradation independently without the effect of each other. The hole injection during the source-side Fowler-Nordheim (FN) erase is responsible for the erase degradation. The interface-state generation during channel hot electron (CHE) programming appears to be the dominant degradation mechanism. Unlike the conventional methods of applying a constant voltage stress on the FG transistor, the dynamic change of FG potential during program or erase cycles was taken into account in our method. As a result, the trapped oxide charge density and interface-state profile in the tunnel oxide are significantly different from those obtained by the conventional methods View full abstract»

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  • To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment

    Page(s): 2769 - 2776
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    The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH3/N2O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O2-grown bottom oxide. In post-deposition treatment, increasing NH3 nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N2O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH3 nitridation step View full abstract»

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  • Traditional and novel vacuum electron devices

    Page(s): 2929 - 2937
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    This paper describes some vacuum devices - including conventional and unique multibeam O-type amplifiers and oscillators in the microwave, millimeter wave, and submillimeter wavelength regions of the spectrum, and miniature injection locked M-type amplifiers. Main parameters and operational characteristics are presented. The paper includes a description of synthesis software, which uses "trained" analytical expressions. These codes enable the optimum electrical design and device geometry to be expeditiously determined during the first phase of development View full abstract»

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  • Metamorphic InP/InGaAs heterojunction bipolar transistors on GaAs substrate: DC and microwave performances

    Page(s): 2671 - 2676
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    High-performance InP/In0.53Ga0.47As metamorphic heterojunction bipolar transistors (MHBTs) on GaAs substrate have been fabricated using InxGa1-xP strain relief buffer layer grown by solid-source molecular beam epitaxy (SSMBE). The MHBTs exhibited a dc current gain over 100, a unity current gain cutoff frequency (fT) of 48 GHz and a maximum oscillation frequency (fMAX) of 42 GHz with low junction leakage current and high breakdown voltages. It has also been shown that the MHBTs have achieved a minimum noise figure of 2 dB at 2 GHz (devices with 5×5 μm 2 emitter) and a maximum output power of 18 dBm at 2.5 GHz (devices with 5×20 μm2 emitter), which are comparable to the values reported on the lattice-matched HBTs (LHBTs). The dc and microwave characteristics show the great potential of the InP/InGaAs MHBTs on GaAs substrate for high-frequency and high-speed applications View full abstract»

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  • Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs

    Page(s): 2861 - 2869
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    A one-dimensional (1-D) analytic solution is derived for an undoped (or lightly doped) double-gate (DG) MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution is applied to both symmetric and asymmetric DG MOSFETs to obtain closed forms of band bending and inversion charge as a function of gate voltage and silicon thickness. It is shown that for the symmetric DG device, "volume inversion" only occurs under subthreshold conditions, with a slightly negative impact on performance. Comparisons under the same off-state conditions show that the on-state inversion charge density of an asymmetric DG with one channel is only slightly less than that of a symmetric DG with two channels, if the silicon film is thin. From the analytic solutions, explicit expressions for the various components of the equivalent capacitance circuit are derived for symmetric and asymmetric DG devices. These help gain an insight into the electrostatic coupling between the back gate and the front channel in the asymmetric case. Finally, the gate work function requirements are quantified for symmetric and asymmetric DG CMOS, based on threshold voltage considerations View full abstract»

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  • Theory of 1/f noise currents in semiconductor devices with one-dimensional geometry and its application to Si Schottky barrier diodes

    Page(s): 2875 - 2883
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    A theory of the short-circuit 1/f noise currents in semiconductor devices with one-dimensional geometry is derived using the noise current density equation with the 1/f noise source term based on the Hooge's empirical 1/f noise relation. It is shown that both the number fluctuation model and the mobility fluctuation model for 1/f noise give the same result. The newly derived 1/f formula is shown to explain the measured 1/f noise currents of Si Schottky barrier rectifiers under both forward and reverse bias conditions with a single set of Hooge parameters of electrons and holes for a given device View full abstract»

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  • (AlxGa1-x)0.5In0.5P/In 0.15Ga0.85As (x=0, 0. 3, 1. 0) heterostructure doped-channel FETs for microwave power applications

    Page(s): 2906 - 2910
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    The quaternary (AlxGa1-x)0.5In 0.5P (0⩽×⩽1) compounds on GaAs substrates are important materials used as a Schottky layer in microwave devices. In this report, we systematically investigated the electrical properties of quaternary (AlxGa1-x)0.5In0.5P materials and concluded that the best composition for improving the device performance is by substituting 30% (x=0.3) of Ga atoms for Al atoms in GaInP material. The Schottky barrier heights (φB) of (Al xGa1-x)0.5In0.5P layers were 0.85~1.00 eV. We successfully realized the (AlxGa1-x )0.5In0.5P/In0.15Ga0.85 As (x=0, 0.3, 1.0) doped-channel FETs (DCFETs) and demonstrated excellent dc, microwave, and power characteristics View full abstract»

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  • A new optoelectronic integrated device for light-amplifying optical switch (LAOS)

    Page(s): 2732 - 2739
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    A new optoelectronic integrated device is proposed for a light-amplifying optical switch (LAOS). The device is composed of an optical field-effect transistor (OPFET) in series with a light source which may be either a double heterostructure light-emitting diode (LED) or laser diode (LD). A quantitative circuit model for the proposed LAOS is presented and theoretical investigation is carried out for developing a current-voltage (I-V) relation for the device. It is shown analytically that switching action takes place from a low current state to a high current state through a region of negative differential resistance (NDR) when a voltage greater than the breakover voltage is applied View full abstract»

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  • Edge hole direct tunneling leakage in ultrathin gate oxide p-channel MOSFETs

    Page(s): 2790 - 2795
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    This paper examines the edge direct tunneling (EDT) of holes from p+ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness TOX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field EOX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates EOX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once EOX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected View full abstract»

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  • Impact-ionization and noise characteristics of thin III-V avalanche photodiodes

    Page(s): 2722 - 2731
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    It is, by now, well known that McIntyre's localized carrier-multiplication theory cannot explain the suppression of excess noise factor observed in avalanche photodiodes (APDs) that make use of thin multiplication regions. We demonstrate that a carrier multiplication model that incorporates the effects of dead space, as developed earlier by Hayat et al. provides excellent agreement with the impact-ionization and noise characteristics of thin InP, In0.52 Al0.48As, GaAs, and Al0.2Ga0.8As APDs, with multiplication regions of different widths. We outline a general technique that facilitates the calculation of ionization coefficients for carriers that have traveled a distance exceeding the dead space (enabled carriers), directly from experimental excess-noise-factor data. These coefficients depend on the electric field in exponential fashion and are independent of multiplication width, as expected on physical grounds. The procedure for obtaining the ionization coefficients is used in conjunction with the dead-space-multiplication theory (DSMT) to predict excess noise factor versus mean-gain curves that are in excellent accord with experimental data for thin III-V APDs, for all multiplication-region widths View full abstract»

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  • Design rules for field plate edge termination in SiC Schottky diodes

    Page(s): 2659 - 2664
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    Practical design of silicon carbide (SiC) Schottky diodes incorporating a field plate necessitates an understanding of how the addition of the field plate affects the performance parameters and the relationship between the diode structure and diode performance. In this paper, design rules are presented for SiC Schottky diodes that incorporate field plate edge termination. The use of an appropriate field plate edge termination can improve the reverse breakdown voltage of a SiC Schottky diode by a factor of two. Reverse breakdown voltage values can be obtained that are up to 88% of the theoretical maximums View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology