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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan. 2002

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  • International Symposium on Physical Design (ISPD)

    Publication Year: 2002
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    The following topics are dealt with: physical design of VLSI systems; interconnect performance prediction and optimization; design for manufacturability; floorplanning; congestion estimation; signal integrity View full abstract»

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  • Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters

    Publication Year: 2002 , Page(s): 50 - 62
    Cited by:  Papers (24)  |  Patents (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    Trends in complementary metal-oxide-semiconductor (CMOS) technology and very large scale integration architectures are causing interconnect to play an increasing role in overall performance, power consumption, and design effort. Traditionally, repeaters are used for driving long onchip interconnects. However, recent studies indicate that repeaters are using increasing area, power, and design resources and are inherently limited in how much they can improve the performance (Adler and Friedman, 1998), (Sylvester and Keutzer, 1999), (Cong and Pan, 1999). The unidirectionality of repeaters also limits their applicability in multisourced lines. This paper presents a new circuit called the Booster that compares favorably with repeaters for driving long lines in terms of area, performance, power, and placement sensitivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are reduced and peak power is drastically reduced compared to repeaters, thus, improving signal integrity and mitigating inductive effects. Boosters are shown to be more than 20% faster for driving a variety of interconnect loads over conventional repeaters in a 0.16-μm CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths and, hence, saving on area, power, and placement effort. Computer-aided design tools for global interconnect synthesis need to support a wider variety of circuit techniques such as boosters. Other exotic circuit techniques such as differential, dynamic, or low-swing techniques require significantly more custom circuit design, noise analysis, extra timing signals, or extra power supplies and are, hence, cumbersome for automatic interconnect synthesis tools. In contrast, the proposed boosters can be inserted on lines in a straightforward manner much like repeaters. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into an interconnect synthesis tool. We formulate design rules that determine: 1) the number of boosters needed; 2) their placements; and 3) device sizes for driving a given interconnect load. The primary objective function is minimizing delay and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement sensitivity analysis comparing boosters and repeaters is used to study the effects of realistic placement constraints that arise in microprocessor floorplans. We conclude by discussing various design tradeoffs between repeater and booster-based interconnect designs. We then present other potential applications of boosters in domino logic designs, multisource/multisink buses, and field programmable gate array interconnection network designs in addition to conventional point-to-point interconnection lines View full abstract»

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  • An efficient and regular routing methodology for datapath designs using net regularity extraction

    Publication Year: 2002 , Page(s): 93 - 101
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    We present a new detailed routing methodology specifically designed for datapath layouts. In typical state-of-the-art microprocessor designs, datapaths comprise about 70% of the logic (excluding caches). However, most logic and layout synthesis research has targeted random-logic portions of the design. In general, techniques for random-logic placement and routing do not produce good results for datapath layouts. Although research on datapath placement and global routing has been reported, very little research has been reported in the area of detailed routing for datapaths. Our datapath routing methodology exploits the unique feature of datapaths, namely, their regularity. Datapaths typically comprise regular structures (or bit slices), which are replicated. The interconnections between these replicated bit slices are also typically very regular. Our datapath routing methodology utilizes new techniques to extract interconnect regularity among bit slices. We define a net cluster, which is collection of similarly structured nets present across different bit slices. We introduce two clustering schemes (footprint-driven clustering and instance-driven clustering) to extract such net clusters. Using these net clusters, we select one representative bit slice to perform a strap-based routing (which optimally finds the shortest path between two points if that path is available) on a member net of each net cluster. Then for each such net, we propagate its route to all other nets in its net cluster. Our algorithm is unique in that it performs the detailed routing on a single bit slice and infers the routing for all bit slices using the notion of net clusters. Since we only route a small fraction of nets present in the design, significant speedup is obtained. We demonstrate at least six times speedup for industrial 32- and 64-bit datapath designs. The regularity of the routes across the bit slices results in more predictable timing characteristics for the resulting layout View full abstract»

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  • Estimating routing congestion using probabilistic analysis

    Publication Year: 2002 , Page(s): 32 - 41
    Cited by:  Papers (27)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    Design routability is a major concern in the application-specific design flow, particularly with today's increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed net list. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are its accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with postroute congestion and present experimental results of subsequent congestion minimization based on this algorithm View full abstract»

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  • An analysis of the wire-load model uncertainty problem

    Publication Year: 2002 , Page(s): 23 - 31
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (193 KB) |  | HTML iconHTML  

    Traditional integrated-circuit (IC) design methodologies have used wire-load models during logic synthesis to estimate the expected impact of the metal wiring on the gate delays. These models are based on wire-length statistics from legacy designs to facilitate a top-down IC design flow process. Recently, there has been increased concern regarding the efficacy of wire-load models as deep-submicrometer (DSM) interconnect parasitics begin to dominate the delay of digital IC logic gates. Some technology projections (Sylvester and Keutzer, 1998) have suggested that wire-load models will remain effective to block sizes on the order of 50 000 gates. This suggests that existing top-down synthesis methodologies will not have to be changed substantially since this is approximately the maximum size for which logic synthesis is effective. However, our analyses on production designs show that the problem is not quite so straightforward and the efficacy of synthesis using wire-load models depends upon technology data as well as specific characteristics of the design and the granularity of available physical information. We analyze these effects and dependencies in detail in this paper and draw some conclusions regarding the future challenges associated with top-down IC design and block synthesis, in particular, in the DSM design era View full abstract»

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  • Dummy-feature placement for chemical-mechanical polishing uniformity in a shallow-trench isolation process

    Publication Year: 2002 , Page(s): 63 - 71
    Cited by:  Papers (15)  |  Patents (41)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (343 KB) |  | HTML iconHTML  

    Manufacturability of a design that is processed with shallow-trench isolation (STI) depends on the uniformity of the chemical-mechanical polishing (CMP) step in STI. The CMP step in STI is a dual-material polish for which all previous studies on dummy-feature placement for single-material polish by Kahng et al. (1999), Tian et al. (2000), and Chen et al. (2000) are not applicable. Based on recent semiphysical models of polish-pad bending by Ouma et al (1998), local polish-pad compression by Grillaert (1999) and Smith (1999), and different polish rates for materials present in a dual-material polish by Grillaert (1999) and Tugbawa et al. (1999), this paper derives a time-dependent relation between post-CMP topography and layout pattern density for CMP in STI. Using the dependencies derived, the first formulation of dummy-feature placement for CMP in STI is given as a nonlinear-programming problem. An iterative approach is proposed to solve the dummy-feature placement problem. Computational experience on four layouts from Motorola is given View full abstract»

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  • Congestion estimation during top-down placement

    Publication Year: 2002 , Page(s): 72 - 80
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    Congestion is one of the fundamental issues in very large scale integration physical design. In this paper, we propose two congestion-estimation approaches for early placement stages. First, we theoretically analyze the peak-congestion value of the design and experimentally validate the estimation approach. Second, we estimate regional congestion at the early stages of top-down placement. This is done by combining the wire-length distribution model and interregion wire estimation. Both approaches are based on the well-known Rent's rule, which is previously used for wirelength estimation. This is the first attempt to predict congestion using Rent's rule. The estimation results are compared with the layout after placement and global routing. Experiments on large industry circuits show that the early congestion estimation based on Rent's rule is a promising approach View full abstract»

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  • Consistent floorplanning with hierarchical superconstraints

    Publication Year: 2002 , Page(s): 42 - 49
    Cited by:  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    Sequence-pair-based floorplanning has revealed the limit of its usefulness in very large scale integration layout design, the key issue being that it is nonhierarchical and indifferent to the preceding step of partitioning. This paper restructures the sequence pair enhanced to a pair of logic expressions to accept the constraint induced by the previous step - the balanced bipartition. Since the bipartition is hierarchical in nature, the transferred constraint is called the hierarchical superconstraint. Since floorplanning based on this data structure automatically works cooperatively with the partitioning, it is called the consistent floorplanning, which has potential to store all the feasible floorplans under the constraint induced by any balanced binary search. As a typical example, we focus on clock-tree synthesis by H-tree. Experiments are given to show better achievements in length and wire density for module-based circuits and clock trees View full abstract»

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  • Effective enforcement of path-delay constraints in performance-driven placement

    Publication Year: 2002 , Page(s): 15 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudolink is added to connect the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified input-output pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move one cell at a time to its force-equilibrium location assuming all other cells are fixed. The process stops when no cell can be move farther than a threshold distance. Next, cell rows are formed one at a time starting from the top and bottom. After forming these two cell rows (top/bottom), all remaining movable core cells' force-equilibrium locations are updated. The row-formation-and-update process continues until all rows are formed and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial automatic placement-and-route flow. Experimental results on benchmark circuits up to 191-K cell (500-K gate) show that the critical path delay can be improved by as much as 17%. Our layout quality is independent of initial placement. We also study the effect on both layout quality and central processing unit time consumption due to the amount of pseudolinks added. We found that the introduction of pseudolink indeed significantly improves the layout quality. We also empirically demonstrated that the proposed approach is effective in reducing the total half-perimeter wirelength metric View full abstract»

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  • Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning

    Publication Year: 2002 , Page(s): 81 - 92
    Cited by:  Papers (73)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (271 KB) |  | HTML iconHTML  

    We investigate the problem of decoupling capacitance (decap) allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given and consider the decap placement as a postfloorplan step. Second, we consider the decap placement as an integral part of a floorplanning methodology (noise-aware floorplanning). In both cases, the objective is to minimize the floorplan area while suppressing the power supply noise below the specified limit. Experimental results on MCNC benchmark circuits show that, for postfloorplan decap placement, the white space allocated for decap is about 6%-9% of the chip area for the 0.25-μm technology. The power-supply noise is kept below the specified limit. Compared to postfloorplan approach, the peak power-supply noise can be reduced by as much as 40% and the decap budget can be reduced by as much as 21% by using noise-aware floorplanning methodology. The total area is also reduced due to the reduced total decap budget gained from reduced power supply noise View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu