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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 9 • Date Sep 2001

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Displaying Results 1 - 11 of 11
  • A low-power array multiplier using separated multiplication technique

    Publication Year: 2001 , Page(s): 866 - 871
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB) |  | HTML iconHTML  

    The authors propose a separated multiplication technique that can be used in digital image signal processing such as finite impulse response (FIR) filters to reduce the power dissipation. Since the 2-D image data have high spatial redundancy, such that the higher bits of input pixels are hardly changed, the redundant multiplication of higher bits is avoided by separating multiplication into higher and lower parts. The calculated values of the higher bits are stored in memory cells, caches, such that they can be reused when a cache hit occurs. Therefore, the dynamic power is reduced by about 14% in multipliers by using the proposed separated multiplication technique (SMT) and in a 1-D 4-tap FIR filter by about 10% View full abstract»

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  • Noise optimization of an inductively degenerated CMOS low noise amplifier

    Publication Year: 2001 , Page(s): 835 - 841
    Cited by:  Papers (103)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels View full abstract»

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  • A, multifrequency range digital sinusoidal oscillator with high resolution and uniform frequency spacing

    Publication Year: 2001 , Page(s): 872 - 876
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    In this work, a high-resolution and multifrequency range complex digital sinusoidal oscillator with uniform frequency spacing is proposed and its performance is evaluated. The proposed oscillator structure is capable of generating both the real and imaginary components of a complex exponential digital signal. The proposed oscillator utilizes two integrators with adjustable gains and two multipliers and can be implemented on already available digital signal processors. The frequency resolution of the proposed oscillator is shown to be adjustable and is superior to that of the direct-form digital oscillator. Simulation results are presented to verify the analysis and demonstrate the quality of the generated sinusoids measured in terms of total harmonic distortion View full abstract»

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  • A novel structure of LWOS filters based on threshold decomposition

    Publication Year: 2001 , Page(s): 857 - 862
    Cited by:  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    In this work, we discuss the restoration of a signal corrupted by additive noise. We aim to develop a smoothing filter which can utilize both the rank- and temporal-order information of the input data. It is well known that the LWOS-filter is one nonlinear filter which can utilize both kinds of information. However, the LWOS filter suffers from rapid growth in the number of parameters as the window size increases. It is impossible to design LWOS filters with a window larger than 5×5. This window size limitation is a major drawback for image processing. This work presents a novel form of LWOS filter, called the modified LWOS (M-LWOS) filter. M-LWOS filters are defined in the threshold decomposition domain. A M-LWOS filter with arbitrary window size can be easily designed. We present a design method for the M-LWOS filter and show the effectiveness of the proposed filter View full abstract»

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  • Quantization noise improvement in a hybrid distributed-neuron ANN architecture

    Publication Year: 2001 , Page(s): 842 - 846
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (129 KB) |  | HTML iconHTML  

    This work explores a useful self-scaling property of a hybrid (analog-digital) artificial neural network architecture based on distributed neurons. In conventional sigmoidal neural networks with lumped neurons, the effect of weight quantization errors becomes more noticeable at the output as the network becomes larger. However, it is shown here based on a stochastic model that the inherent self-scaling property of a distributed-neuron architecture controls the output quantization noise (error) to signal ratio as the number of inputs to an Adaline increases. This property contributes to a robust hybrid VLSI architecture consisting of digital synaptic weights and analog distributed neurons View full abstract»

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  • Programmable 1-D rank filter of O(1) time complexity

    Publication Year: 2001 , Page(s): 876 - 881
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    An efficient architecture and circuit implementation for programmable rank filtering is presented. The circuit ranks a one-dimensional signal in an amount of time independent of the number of signal values and the rank number. The operation is based on one MIN and one MAX filter, and can be efficiently implemented using winner-take-all circuits of O(1) time complexity and O(n) hardware complexity. SPICE simulations and experimental results from a fabricated CMOS chip are included View full abstract»

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  • A modified shuffle-free architecture for linear convolution

    Publication Year: 2001 , Page(s): 862 - 866
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB) |  | HTML iconHTML  

    This paper presents a class of modified parallel very large scale integration architectures for linear convolution in shuffle-free forms. The proposed algorithms show that for 1-D convolution, the number of lower-order convolutions can be reduced from three to two allowing a hardware saving without slowing down the processing speed. The proposed partitioning strategy results in a core of data-independent convolution computations. Such computations can be overlapped in software pipelines, super pipelines, or executed concurrently on multiple functional units in a DSP chip View full abstract»

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  • Low-voltage CMOS frequency synthesizer for ERMES pager application

    Publication Year: 2001 , Page(s): 826 - 834
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    A low-voltage frequency synthesizer fabricated with a 0.35-μm standard CMOS technology is presented. A 1 V dual-modulus prescaler using the dynamic back-gate forward bias method has been developed for low-voltage operation. The prescaler, including a preamplifier, measured at 1 V supply voltage has a maximum operating frequency of 170 MHz, and its power dissipation is only 0.9 mW. The voltage-controlled oscillator (VCO) in the frequency synthesizer is an LC-tank based oscillator. When locked at the oscillation frequency of 148 MHz, the measured phase noise of the VCO is -106 dBc/Hz at -100-kHz from the carrier. The whole power consumption of the frequency synthesizer is 10.5 mW View full abstract»

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  • Low 1/f noise CMOS active mixers for direct conversion

    Publication Year: 2001 , Page(s): 846 - 850
    Cited by:  Papers (38)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    The analysis of direct conversion CMOS active mixers tailored to ReFlex standard is presented. To minimize 1/f noise, the switching stage pMOS devices have large area, low biasing current. pMOS and nMOS transconductors shunted together form the input stage. A 0.35-μm prototype performs at 900 MHz as follows: 18 dB SSB NF averaged in the 100 Hz-3 kHz band, 18 dB gain, -4-dBm IIP3, 30-dBm IIP2 with 6 mA from 2.7-V supply View full abstract»

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  • Dynamic pipeline design of an adaptive binary arithmetic coder

    Publication Year: 2001 , Page(s): 813 - 825
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB) |  | HTML iconHTML  

    Arithmetic coding is an attractive technique for lossless data compression but it tends to be slow. In this paper, a dynamic pipelined very large scale integration architecture with high performance for on-line adaptive binary arithmetic coding is presented. To obtain a high throughput pipelined architecture, we first analyze the computation flow of the coding algorithm and modify the operations whose data and/or control dependencies cause the difficulties in pipelining. Then, a novel technique called dynamic pipelining is developed to pipeline the coding process with variant (or run-time determined) pipeline latencies (or data initialization intervals) efficiently. As for data path design, a systematic design methodology of high level synthesis and a lower-area but faster fixed-width multiplier are applied, which implement the architecture with a little additional hardware. The dynamic pipelined architecture has been designed and simulated in Verilog HDL, and its layout has also been implemented with the 0.8-μm SPDM CMOS process and the ITRI-CCL cell library. Its simulated compression speeds under working frequencies of 25 and 50 MHz are about 6 and 12.5 Mb/s, respectively. About two times the speedup with 30% hardware overhead relative to the original sequential realisation is achieved View full abstract»

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  • A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation

    Publication Year: 2001 , Page(s): 850 - 857
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB) |  | HTML iconHTML  

    A mathematical approximation for the sine function is proposed which is so close to the sine function that it satisfies the accuracy requirements for sine computation in a typical sine-output direct digital frequency synthesizers (DDS). Then, it is shown that the proposed approximation is realizable by standard digital circuitry, so, a novel ROM-less architecture for sine-output DDS is developed, optimized, and implemented. Experimental results for the implemented ROM-less sine-output DDS are in complete agreement with simulation results in showing that the approximation error will cause harmonic levels below the spurious levels associated with the output quantization error. Another important advantage of the proposed architecture is that it dispenses with ROM, so it can be easily pipelined in order to be as fast as is required View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope