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Circuits and Systems for Video Technology, IEEE Transactions on

Issue 11 • Date Nov 2001

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Displaying Results 1 - 6 of 6
  • An efficient wavelet-based deblocking algorithm for highly compressed images

    Publication Year: 2001 , Page(s): 1193 - 1198
    Cited by:  Papers (31)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB)  

    A new post-processing method is proposed in the wavelet domain for the suppression of blocking artifacts in compressed images. The novelty of our method is that we can obtain soft-threshold values based on the difference between the wavelet transform coefficients of the image blocks and the coefficients of the entire image to threshold high-frequency wavelet coefficients in different subbands using different values and strategies. The threshold value is made adaptive to different images and characteristics of blocking artifacts. In particular the new method is robust, fast, and works remarkably well for different discrete cosine transform-based compressed images at low bit rates. The method is nonlinear, computationally efficient, and spatially adaptive. Another advantage of the new method is that it retains sharp features in the images since it only removes artifacts. Experimental results show that the proposed method can achieve a significantly improved visual quality and also increase the PSNR in the output image. Our method also performs better than algorithms based on overcomplete wavelet presentation for images containing a large portion of texture View full abstract»

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  • High-performance and low-power memory-interface architecture for video processing applications

    Publication Year: 2001 , Page(s): 1160 - 1170
    Cited by:  Papers (26)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (310 KB) |  | HTML iconHTML  

    To improve memory bandwidth and power consumption in video applications, a new memory-interface architecture is proposed. The architecture adopts an array address-translation technique to utilize the fact that video processing algorithms have regular memory-access patterns. Since the translation can minimize the number of overhead cycles needed for row-activations in synchronous DRAM (SDRAM), we can improve the memory bandwidth and energy consumption significantly. The features of SDRAM and memory-access patterns of video processing applications are considered to find a suitable address translation. Compared to the conventional linear translation, experimental results show that the proposed architecture reduces about 89% of row-activations and increases the memory bandwidth by 50%. In addition, the proposed architecture reduces the energy consumption by 30% on the average View full abstract»

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  • A robust model generation technique for model-based video coding

    Publication Year: 2001 , Page(s): 1188 - 1192
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    In conventional model-based coding schemes, predefined static models are generally used. These models cannot adapt to new situations, and hence, they have to be very specific and cannot be generated from a single generic model even though they are very similar. We present a model-generation technique that can gradually build a model and dynamically modify it according to new video frames scanned. The proposed technique is robust to the object's orientation in the view and can be efficiently implemented with a parallel processing technique. As a result, the proposed technique is more attractive to the practical use of model-based coding techniques in real applications View full abstract»

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  • A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array

    Publication Year: 2001 , Page(s): 1149 - 1159
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    A new recursive algorithm with hardware complexity of O(log2 N) is derived for fast computation of N×N 2-D discrete cosine transforms (2-D DCTs). It first converts the original 2-D data matrices into 1-D vectors and then employs different partition methods for the input and output indices in the 1-D vector space. Afterward, the algorithm computes the corresponding 2-D complex DCT (2-D CCT) and then uses a post-addition step to produce simultaneously two 2-D DCT outputs. The decomposed form of the 2-D recursive algorithm looks like a radix-4 fast Fourier transform algorithm. The common entries in each row of the butterfly-like matrix are factored out in order to reduce the number of multipliers needed during implementation. A new linear architecture for the derived algorithm is presented which leads to a hardware-efficient architectural design requiring only log2N complex multipliers plus 3log2N complex adders/subtractors for the computation of a 2-D N×N CCT View full abstract»

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  • Robust image transmission with bidirectional synchronization and hierarchical error correction

    Publication Year: 2001 , Page(s): 1183 - 1187
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB) |  | HTML iconHTML  

    We present a novel joint-source and channel image-coding scheme for noisy channel transmission. The proposed scheme consists of two innovative components: (1) intelligent bidirectional synchronization and, (2) layered bit-plane error protection. The bidirectional synchronization is able to recover the coding synchronization when any single or even when two consecutive synchronization codes are corrupted by the channel noise. With synchronized partition, unequal error protection for each bit plane can be designed based on the analysis of bit-plane error sensitivity for compressed image data transmission over noisy channels. Experimental results over extensive channel simulations show that the proposed scheme outperforms the well-known approach proposed by Sherwood and Zeger (see IEEE Signal Processing Lett., vol.4, p.189-91, 1997) View full abstract»

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  • Video object tracking with a sequential hierarchy of template deformations

    Publication Year: 2001 , Page(s): 1171 - 1182
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    We have developed a new contour-based tracking algorithm that uses a sequence of template deformations to model and track generic video objects. We organize the deformations into a hierarchy: globally affine deformations, piecewise (locally) affine deformations, and arbitrary smooth deformations (snakes). This design enables the algorithm to track objects whose pose and shape change in time compared to the template. If the object is not a rigid body, we model the temporal evolution of its shape by updating the entire template after each video frame; otherwise, we only update the pose of the object. Experimental results demonstrate that our method is able to track a variety of video objects, including those undergoing rapid changes. We quantitatively compare our algorithm with its constituent pieces (e.g., the snake algorithm) and show that the complete algorithm can track objects with moving parts for a longer duration than partial versions of the hierarchy. It could be benefited from a higher level algorithm to dynamically adjust the parameters and template deformations to improve the segmentation accuracy further. The hierarchical nature of this algorithm provides a framework that offers a modular approach for the design and enhancement of future object-tracking algorithms View full abstract»

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Aims & Scope

The emphasis is focused on, but not limited to:
1. Video A/D and D/ A
2. Video Compression Techniques and Signal Processing
3. Multi-Dimensional Filters and Transforms
4. High Speed Real-Tune Circuits
5. Multi-Processors Systems—Hardware and Software
6. VLSI Architecture and Implementation for Video Technology 

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Dan Schonfeld
Multimedia Communications Laboratory
ECE Dept. (M/C 154)
University of Illinois at Chicago (UIC)
Chicago, IL 60607-7053
tcsvt-eic@tcad.polito.it

Managing Editor
Jaqueline Zelkowitz
tcsvt@tcad.polito.it