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Proceedings of the IEEE

Issue 11 • Nov. 2001

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Displaying Results 1 - 14 of 14
  • Special issue on microprocessor architecture and compiler technology

    Publication Year: 2001, Page(s):1547 - 1549
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    Freely Available from IEEE
  • Proceedings of the IEEE: 2002 - Celebrating ninety years of new technology! [Editorial]

    Publication Year: 2001, Page(s):1550 - 1552
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    Freely Available from IEEE
  • Hardware/compiler codevelopment for an embedded media processor

    Publication Year: 2001, Page(s):1694 - 1709
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    Embedded and portable systems running multimedia applications create a new challenge for hardware architects. A microprocessor for such applications needs to be easy to program like a general-purpose processor and have the performance and power efficiency of a digital signal processor. This paper presents the codevelopment of the instruction set, the hardware, and the compiler for the Vector IRAM ... View full abstract»

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  • Dynamic techniques for load and load-use scheduling

    Publication Year: 2001, Page(s):1621 - 1637
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    Modern microprocessors employ dynamic instruction scheduling to select independent instructions for parallel execution. Good scheduling of loads is crucial, since the long latency of some loads makes them likely to degrade performance. A good scheduler attempts to issue loads as early as possible. Scheduling loads is not simple. First, safely resolving a load's input dependences can be done only a... View full abstract»

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  • Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

    Publication Year: 2001, Page(s):1560 - 1575
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB) | HTML iconHTML

    Semiconductor technology scaling provides faster and more plentiful transistors to build microprocessors, and applications continue to drive the demand for more powerful microprocessors. Weaving the "raw" semiconductor material into a microprocessor that offers the performance needed by modern and future applications is the role of computer architecture. This paper overviews some of the microarchi... View full abstract»

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  • Compiling for EPIC architectures

    Publication Year: 2001, Page(s):1676 - 1693
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (197 KB) | HTML iconHTML

    Designing compilers for Explicitly Parallel Instruction Computing (EPIC.) architectures presents challenges substantially different from those encountered in designing compilers for traditional sequential architectures. These challenges are addressed not only by employing new optimizations that are specific to EPIC, but also by employing new ways to architect compilers. EPIC architectures provide ... View full abstract»

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  • Understanding branches and designing branch predictors for high-performance microprocessors

    Publication Year: 2001, Page(s):1610 - 1620
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (174 KB) | HTML iconHTML

    Branch prediction is important in high-performance processors and its importance continues to grow. In the drive for higher execution frequencies, pipelines are lengthened and memory latencies are increased. This increases the cost of branch mispredictions. In this paper we describe some behavior patterns of branches. We believe that understanding the behavior of branches is helpful when designing... View full abstract»

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  • Advances and future challenges in binary translation and optimization

    Publication Year: 2001, Page(s):1710 - 1722
    Cited by:  Papers (13)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    Binary translation and optimization have achieved a high profile in recent years. Binary translation has several potential attractions. While still in its early stages, could binary translation offer a new way to design processors, i.e. is it a disruptive technology? This paper discusses this question, examines some future possibilities for binary translation, and then gives an overview of selecte... View full abstract»

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  • Instruction scheduling for instruction level parallel processors

    Publication Year: 2001, Page(s):1638 - 1659
    Cited by:  Papers (22)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB) | HTML iconHTML

    Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without "heroic" compiling techniques, most such processors fall far short of their performan... View full abstract»

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  • Requirements, bottlenecks, and good fortune: agents for microprocessor evolution

    Publication Year: 2001, Page(s):1553 - 1559
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (78 KB) | HTML iconHTML

    The first microprocessor the Intel 4004, showed up in 1971. It contained 2300 transistors and operated at a clockfrequency of 108 kHz. Today, 30 years later the microprocessor contains almost 200 million transistors, operating at a frequency of more than 1 GHz. In five years, those numbers are expected to grow to more than a billion transistors on a single chip, operating at a clockfrequency of fr... View full abstract»

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  • Low-power design for embedded processors

    Publication Year: 2001, Page(s):1576 - 1587
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Minimization of power consumption in portable and battery powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor... View full abstract»

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  • Lighting your country house

    Publication Year: 2001, Page(s):1723 - 1726
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    Today we assume that electricity for our lights is readily available from the mains, but a hundred years ago that was not necessarily the case. Your correspondent has recently been looking at a large house in a rural part of England where, in the 1890s, the owner decided to adopt electric light, and consequently had to install his own generating plant. Now the house is open to the public, and the ... View full abstract»

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  • Program decision logic optimization using predication and control speculation

    Publication Year: 2001, Page(s):1660 - 1675
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    The mainstream arrival of predication, a means other than branching of selecting instructions for execution, has required compiler architects to reformulate fundamental analyses and transformations. Traditionally, the compiler has generated branches straightforwardly to implement control flow designed by the programmer and has then performed sophisticated "global" optimizations. to move and optimi... View full abstract»

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  • Instruction fetch architectures and code layout optimizations

    Publication Year: 2001, Page(s):1588 - 1609
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (407 KB) | HTML iconHTML

    The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing a higher performance processor implies balancing all the pipeline stages to ensure that overall performance is not dominated by any of them. This means that a faster executio... View full abstract»

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H. Joel Trussell
North Carolina State University