IEE Proceedings - Computers and Digital Techniques

Issue 45 • Jul/Sep 2001

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Displaying Results 1 - 6 of 6
  • Performance analyses on the generalised buddy system

    Publication Year: 2001, Page(s):167 - 175
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (797 KB)

    For the past three decades (1970-2000), the buddy system has been the method of choice for memory allocation because of its speed and simplicity. However, the software realisation indicates that the buddy system incurs the overhead of internal fragmentation, external fragmentation, and memory traffic due to splitting and coalescing memory blocks. The paper presents a thorough analysis of the buddy... View full abstract»

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  • VLSI architecture for quadtree-based fractal image coding

    Publication Year: 2001, Page(s):141 - 146
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (512 KB)

    A VLSI architecture for flexible-size fractal image coding is proposed. The main features of this architecture are that it is capable of performing fractal image coding based on quadtree partitioning without external memory for the fixed domain pool and uses only local data communication. Since large domain blocks consist of small domain blocks, the calculations of distortion for all kinds of doma... View full abstract»

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  • Minimising power dissipation in partial scan sequential circuits

    Publication Year: 2001, Page(s):163 - 166
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (387 KB)

    Recently a new test application strategy for minimising of power dissipation during test applications in full scan sequential circuits was proposed. This paper investigates its applicability to partial scan sequential circuits. It is shown that, when compared to full scan sequential circuits, partial scan not only reduces the test area overhead and test application time, but also reduces the power... View full abstract»

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  • Performance analysis of three implementation strategies for distributed lock management

    Publication Year: 2001, Page(s):176 - 187
    Cited by:  Papers (3)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (849 KB)

    A distributed lock manager (DLM) provides distributed applications with a convenient means of synchronising their accesses to shared resources. The authors present a performance study of three different implementation strategies for a DLM, considering both the layout of the lock database (centralised or distributed) and the strategy used to assign lock masters (static or dynamic). For each impleme... View full abstract»

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  • Low power state assignment and flipflop selection for finite state machine synthesis - a genetic algorithmic approach

    Publication Year: 2001, Page(s):147 - 151
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (449 KB)

    Current renewed emphasis for more aggressive logic designs with lesser area, delay, and power, demands exploration of alternative avenues that could lead to better designs, albeit at the higher cost of computation. The author explores the avenue of genetic algorithms for a holistic view for synthesis of finite state machines (FSM) targeting power reduction by incorporating both state assignment an... View full abstract»

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  • Hardware compiler realising concurrent processes in reconfigurable logic

    Publication Year: 2001, Page(s):152 - 162
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1130 KB)

    Reconfigurable computers based on field programmable gate array technology allow applications to be realised directly in digital logic. The inherent concurrency of hardware distinguishes such computers from microprocessor-based machines in which the concurrency of the underlying hardware is fixed and abstracted from the programmer by the software model. However, reconfigurable logic provides us wi... View full abstract»

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Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

Full Aims & Scope