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IEEE Transactions on Electronics Packaging Manufacturing

Issue 3 • Date July 2001

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Displaying Results 1 - 11 of 11
  • Editorial

    Publication Year: 2001, Page(s):149 - 150
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    Freely Available from IEEE
  • Abstracts

    Publication Year: 2001, Page(s):151 - 153
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    Freely Available from IEEE
  • An intelligent data mining system for drop test analysis of electronic products

    Publication Year: 2001, Page(s):222 - 231
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    Drop testing is one common method for systematically determining the reliability of portable electronic products under actual usage conditions. The process of drop testing, interpreting results, and implementing design improvements is knowledge-intensive and time-consuming, and requires a great many decisions and judgments on the part of the human designer. To decrease design cycles and, thereby, ... View full abstract»

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  • Feature transformation methods in data mining

    Publication Year: 2001, Page(s):214 - 221
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    The quality of knowledge extracted from a data set can be enhanced by its transformation. Discretization and filling missing data are the most common forms of data transformation. A new transformation method named feature bundling is introduced. A feature bundle involves a set of features in its pure or transformed form. The computational results reported in this paper show that the classification... View full abstract»

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  • Solder wetting in a wafer-level flip chip assembly

    Publication Year: 2001, Page(s):154 - 159
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps o... View full abstract»

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  • Application-specific economic analysis of integral passives in printed circuit boards

    Publication Year: 2001, Page(s):203 - 213
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    This paper presents an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. In this study we assume that integral resistors are printed or plated directly onto wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors, if present, are embedded... View full abstract»

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  • Optimizing the performance of a surface mount placement machine

    Publication Year: 2001, Page(s):160 - 170
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Process planning is an important and integral part of effectively operating a printed circuit board (PCB) assembly system. A PCB assembly system generally consists of different types of placement machines, testing equipment, and material handling equipment. This research develops a new solution approach to determine the component placement sequence and feeder arrangement for a turret style surface... View full abstract»

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  • A systems approach to semiconductor optimization

    Publication Year: 2001, Page(s):171 - 177
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Manufacturing systems optimization is a vast and complex problem. To ensure high yield within a manufacturing system many attributes and goals need to be considered. The authors aim to examine all of these and obtain the most suitable set-up for the manufacturing process. It is the author's view that to truly optimize a manufacturing system, the system needs to be examined as a whole, enabling the... View full abstract»

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  • Optimization of placement by candidate sieving

    Publication Year: 2001, Page(s):178 - 187
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB) | HTML iconHTML

    A new algorithm for standard cell placement problem is presented. It is based on an idea that appropriate step by step reduction of allocatable cells for each component yields a good placement result. This algorithm named candidate sieving is applicable for discrete quadratic assignment problem with some constraint. The results obtained by candidate sieving are compared in terms of wire length and... View full abstract»

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  • Cycle time estimation for printed circuit board assemblies

    Publication Year: 2001, Page(s):188 - 194
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    Competitive pressures continue to force the electronics industry to keep costs down and to reduce the duration of the development cycle for its products. These goals must be accomplished while maintaining the quality of the products and keeping up with the latest technology. In increasing numbers, electronics companies are collaborating with other companies to achieve their business goals and to s... View full abstract»

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  • On the use of yielded cost in modeling electronic assembly processes

    Publication Year: 2001, Page(s):195 - 202
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Yielded cost is defined as cost divided by yield and can be used as a metric for representing an effective cost per good (nondefective) assembly for a manufacturing process. Although yielded cost is not a new concept, it has no consistent definition in engineering literature, and several different formulations and interpretations exist in the context of manufacturing and assembly. In manufacturing... View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University