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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 3 • Date July 2001

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Displaying Results 1 - 11 of 11
  • Editorial

    Page(s): 149 - 150
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    Freely Available from IEEE
  • Abstracts

    Page(s): 151 - 153
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    Freely Available from IEEE
  • Optimizing the performance of a surface mount placement machine

    Page(s): 160 - 170
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    Process planning is an important and integral part of effectively operating a printed circuit board (PCB) assembly system. A PCB assembly system generally consists of different types of placement machines, testing equipment, and material handling equipment. This research develops a new solution approach to determine the component placement sequence and feeder arrangement for a turret style surface mount-placement machine often used in PCB assembly systems. This solution approach can be integrated into a process planning system to reduce assembly time and improve productivity. The algorithm consists of a construction procedure that uses a set of rules to generate an initial component placement sequence and feeder arrangement along with an improvement procedure to improve the initial solution. An industrial case study conducted at Ericsson, Inc., using a Fuji CP4-3 machine and actual PCB data, is presented to demonstrate the performance of the proposed solution approach. The solutions obtained using the proposed solution approach are compared to those obtained using state of the art PCB assembly process optimization software. For all PCBs in the case study, the proposed solution approach yielded lower placement times than the commercial software, thus generating additional valuable production capacity. This research is applicable for both researchers and practitioners in printed circuit board assembly systems View full abstract»

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  • On the use of yielded cost in modeling electronic assembly processes

    Page(s): 195 - 202
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    Yielded cost is defined as cost divided by yield and can be used as a metric for representing an effective cost per good (nondefective) assembly for a manufacturing process. Although yielded cost is not a new concept, it has no consistent definition in engineering literature, and several different formulations and interpretations exist in the context of manufacturing and assembly. In manufacturing, yield is the probability that an assembly is nondefective. To find the effective cost per good assembly that is invested in the manufacturing or assembly process, cost is accumulated and divided by the yield at the end of the process. This paper reviews and correlates existing yielded cost formulations and presents a new approach that enables consistent measurement of sequential process flows. This new approach defines the yielded cost associated with an individual process step (step yielded cost) as the change in the process's yielded cost when the step is removed from the process. This approach is preferred because it incorporates upstream and downstream information and because it provides a prediction of a specific process step's effective cost per good assembly that is independent of step order between steps that scrap defective product View full abstract»

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  • An intelligent data mining system for drop test analysis of electronic products

    Page(s): 222 - 231
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    Drop testing is one common method for systematically determining the reliability of portable electronic products under actual usage conditions. The process of drop testing, interpreting results, and implementing design improvements is knowledge-intensive and time-consuming, and requires a great many decisions and judgments on the part of the human designer. To decrease design cycles and, thereby, the time to market for new products, it is important to have a method for quickly and efficiently analyzing drop test results, predicting the effects of design changes, and determining the best design parameters. Recent advances in data mining have provided techniques for automatically discovering underlying knowledge from large amounts of experimental data. In this paper, an intelligent data mining system named decision tree expert (DTE) is presented and applied to drop testing analysis. The rule induction method in DTE is based on the C4.5 algorithm. In our preliminary experiments, concise and accurate conceptual design rules were successfully generated from drop test data after incorporation of domain knowledge from human experts. The data mining approach is a flexible one that can be applied to a number of complex design and manufacturing processes to reduce costs and improve productivity View full abstract»

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  • Application-specific economic analysis of integral passives in printed circuit boards

    Page(s): 203 - 213
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    This paper presents an application-specific economic analysis of the conversion of discrete passive components (resistors and capacitors) to integral passives that are embedded within a printed circuit board. In this study we assume that integral resistors are printed or plated directly onto wiring layers (as opposed to requiring a dedicated layer), that bypass capacitors, if present, are embedded by dielectric substitution into existing reference plane layers, and that singulated nonbypass capacitors, if present, are embedded using dedicated layer pair addition. The model presented performs three basic analyses. 1) Board size analysis is used to determine board sizes, layer counts, and the number of boards that can be fabricated on a panel. 2) Panel fabrication cost modeling including a cost of ownership model is used to determine the impact of throughput changes associated with fabricating integral passive panels. 3) Assembly modeling is used to determine the cost of assembling all discrete components, and their associated inspection and rework. The combination of these three analyses is used to evaluate size/cost tradeoffs for several example systems including the NEMI hand-held emulator, a picocell board, and a fiber channel card View full abstract»

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  • Cycle time estimation for printed circuit board assemblies

    Page(s): 188 - 194
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    Competitive pressures continue to force the electronics industry to keep costs down and to reduce the duration of the development cycle for its products. These goals must be accomplished while maintaining the quality of the products and keeping up with the latest technology. In increasing numbers, electronics companies are collaborating with other companies to achieve their business goals and to stay competitive. This collaboration has taken the form of outsourcing entire operations and services in addition to outsourcing certain components. Such collaboration and outsourcing efforts result in a distributed manufacturing environment and place increased stress on the information infrastructure, thus requiring firms to implement technological changes in order to compete using these business and enterprise practices. The Electronics Agile Manufacturing Research Institute (EAMRI), Rensselaer Polytechnic Institute, was formed to develop tools to support distributed electronics manufacturing environments. The principal EAMRI-developed technology is based on a distributed, heterogeneous and network-based information system architecture and is called the Virtual Design Environment (VDE). The VDE uses special algorithms along with a distributed database to optimize printed circuit board design. As a part of this effort, the EAMRI has developed a cycle time estimation model that determines the cycle time or time duration for a printed circuit board assembly before its realization. We model the printed circuit board as going through three stages of realization: design, resource planning, and manufacturing. The cycle time model provides an estimate for each phase based on information available about the printed circuit board before that phase has commenced. This model allows for greater flexibility and insight into planning the development process for a board and in allocating the resources to assure that each circuit board meets its schedule. This paper details the development of cycle time estimation models and describes their potential use in a collaborative, distributed manufacturing environment View full abstract»

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  • Optimization of placement by candidate sieving

    Page(s): 178 - 187
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    A new algorithm for standard cell placement problem is presented. It is based on an idea that appropriate step by step reduction of allocatable cells for each component yields a good placement result. This algorithm named candidate sieving is applicable for discrete quadratic assignment problem with some constraint. The results obtained by candidate sieving are compared in terms of wire length and computing time with those obtained by simulated annealing which is considered the most popular method today. In many cases, candidate sieving has yielded shorter wire lengths, which are equal or almost equal to those obtained by simulated annealing, but with much less computing time View full abstract»

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  • Feature transformation methods in data mining

    Page(s): 214 - 221
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    The quality of knowledge extracted from a data set can be enhanced by its transformation. Discretization and filling missing data are the most common forms of data transformation. A new transformation method named feature bundling is introduced. A feature bundle involves a set of features in its pure or transformed form. The computational results reported in this paper show that the classification accuracy of decision rules generated from data sets with feature bundles is enhanced. The proposed concept of feature bundling is applied to a data set from the semiconductor industry View full abstract»

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  • A systems approach to semiconductor optimization

    Page(s): 171 - 177
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    Manufacturing systems optimization is a vast and complex problem. To ensure high yield within a manufacturing system many attributes and goals need to be considered. The authors aim to examine all of these and obtain the most suitable set-up for the manufacturing process. It is the author's view that to truly optimize a manufacturing system, the system needs to be examined as a whole, enabling the whole system to be optimized, not individual sub-systems. This paper describes a three-phase framework for use in optimising electronic manufacturing systems using a systems approach. Phase 1 is the system-modeling phase where a model of the system to be optimized is created. Phase 2 involves system analysis and control. In this phase the focus is on identifying areas of the manufacturing process where analysis and control needs to be undertaken. A collection of techniques can be used systematically to generate such information and provide an understanding of an individual process's capability. These techniques include process capability indices, measurement operation evaluation indices and process failure mode and effect critical analysis. The final phase is used to optimize the system using techniques such as experimental design and response surface models. This paper describes the proposed framework, which has been validated within semiconductor, assembly and printed circuit board manufacturing plants. Within the semiconductor facility one of the stages of the framework investigated was the process capability ratio (PCR), stage IV of the framework. PCR techniques were used to explain the relationship between the technical specification and the production capabilities. Various PCR indices were used such as Cp, Cpk and Cpm and these were generated for various gate turn off thyristor operations. The use of the Cpk indices is illustrated as a means of determining whether the process for gallium diffusion and gallium resistivity are capable View full abstract»

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  • Solder wetting in a wafer-level flip chip assembly

    Page(s): 154 - 159
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    Wafer-level flip chips provide an innovative solution in establishing flip chip as a standard surface mount process. In this paper, the wetting of solder bumps within confining underfill during the reflow of a wafer-level flip chip assembly is addressed. For real time monitoring of an assembly during the reflow process, a system using a high-speed camera is utilized. The collapse of solder bumps on the chip in the vertical direction is found to be a prerequisite of solder wetting. Underfill voids and outgassing are found to cause chip drift and tilt during the reflow process. In addition, symmetry of the underfill flow and fillet formation is identified as a critical factor in maintaining chip to substrate alignment. During solder wetting of the metallization pads on the substrate, the underfill needs to maintain a low viscosity. With the selection of a thermally stable underfill and corresponding process development, wafer-level flip chip assemblies with good solder interconnects are demonstrated View full abstract»

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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University