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Electron Device Letters, IEEE

Issue 10 • Date Oct. 2001

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Displaying Results 1 - 13 of 13
  • AlGaN/AlN/GaN high-power microwave HEMT

    Page(s): 457 - 459
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (62 KB) |  | HTML iconHTML  

    In this letter, a novel heterojunction AlGaN/AlN/GaN high-electron mobility transistor (HEMT) is discussed. Contrary to normal HEMTs, the insertion of the very thin AlN interfacial layer (/spl sim/1 nm) maintains high mobility at high sheet charge densities by increasing the effective /spl Delta/E/sub C/ and decreasing alloy scattering. Devices based on this structure exhibited good DC and RF performance. A high peak current 1 A/mm at V/sub GS/=2 V was obtained and an output power density of 8.4 W/mm with a power added efficiency of 28% at 8 GHz was achieved. View full abstract»

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  • Low-operation voltage of InGaN-GaN light-emitting diodes with Si-doped In/sub 0.3/Ga/sub 0.7/N/GaN short-period superlattice tunneling contact layer

    Page(s): 460 - 462
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB)  

    InGaN/GaN multiple-quantum-well light-emitting diode (LED) structures including a Si-doped In/sub 0.23/Ga/sub 0.77/N/GaN short-period superlattice (SPS) tunneling contact were grown by metalorganic vapor phase epitaxy. In/sub 0.23/Ga/sub 0.77/N/GaN(n/sup +/)-GaN(p) tunneling junction, the low-resistivity n/sup +/-In/sub 0.3/Ga/sub 0.77/N/GaN SPS instead of high-resistivity p-type GaN as a top contact layer, allows the reverse-biased tunnel junction to form an "ohmic" contact. In this structure, the sheet electron concentration of Si-doped In/sub 0.23/Ga/sub 0.77/N/GaN SPS is around 1/spl times/10/sup 14//cm/sup 2/, leading to an averaged electron concentration of around 1/spl times/10/sup 20//cm/sup 3/. This high-conductivity SPS would lead to a low-resistivity ohmic contact (Au/Ni/SPS) of LED. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 2.95 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V. View full abstract»

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  • Impact of silicide formation on the resistance of common source/drain region

    Page(s): 463 - 465
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (53 KB) |  | HTML iconHTML  

    Silicide had been used to reduce the sheet resistance of diffusion region for almost 20 years. However, as the silicided region becomes small, the contact resistance of silicide/silicon interface becomes higher than the resistance of the Si diffusion region such that current may not flow into the silicide layer. The effect of silicide thickness and contact resistivity on the total resistance of the silicided diffusion region was studied by two-dimensional simulation. It is observed that below a threshold length, the resistance of silicided diffusion region is higher than the unsilicided diffusion region if the silicon consumption during silicide formation is taken into consideration. Thinner silicide and lower contact resistivity reduce total resistance and threshold length but the threshold length is still much longer than the typical design rule of poly-Si to poly-Si distance. It is thus recommended to inhibit silicide formation at the common source/drain region at the metal-gate generation. View full abstract»

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  • Active circuits under wire bonding I/O pads in 0.13 μm eight-level Cu metal, FSG low-k inter-metal dielectric CMOS technology

    Page(s): 466 - 468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (94 KB) |  | HTML iconHTML  

    Active circuits in terms of ring oscillator are moved to the place under the wire bonding pads in 0.13 μm full eight-level copper metal complementary metal-oxide-semiconductor process with fluorinated silicate glass low-k inter-metal dielectric. The bond pad with the 12 k/spl Aring/ thick aluminum metal film as a bonding mechanical stress buffer layer is deposited on the topmost copper metal layer. No noticeable degradations in gate delay or cycle time of ring oscillator are detected in a variety of test structures subjected to bonding mechanical stress and thermal cycling stress. This indicates that the underlying process technology may be reliable and manufacturable in placing active circuits under the bonding pads and thereby the die area utility is recovered fully. More evidence is created from transmission line pulsing experiments as well as capacitive-coupling experiments. View full abstract»

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  • Readout circuit in active pixel sensors in amorphous silicon technology

    Page(s): 469 - 471
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (106 KB) |  | HTML iconHTML  

    The most widely used architecture in large area amorphous silicon (a-Si) flat panel imagers is a passive pixel sensor (PPS), which consists of a detector and a readout switch. While the PPS has the advantage of being compact and amenable toward high-resolution imaging, reading small PPS output signals requires external circuitry such as column charge amplifiers that produce additional noise and reduce the minimum readable sensor input signal. This work presents a current mode amorphous silicon active pixel that performs on-pixel amplification of noise-vulnerable sensor input signals to minimize the effect of external readout noise sources associated with "off-chip" charge amplifiers. Preliminary results indicate excellent small signal linearity along with a high and programmable charge gain. View full abstract»

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  • A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

    Page(s): 472 - 474
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB) |  | HTML iconHTML  

    Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9/spl times/10/sup 6/ and also shows the off-state leakage current 100 times lower than those of the conventional ones at V/sub GS/=-15 V and V/sub DS/=10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications. View full abstract»

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  • Enhanced degradation in polycrystalline silicon thin-film transistors under dynamic hot-carrier stress

    Page(s): 475 - 477
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (66 KB) |  | HTML iconHTML  

    We address the mechanisms responsible for the enhanced degradation in the polysilicon thin-film transistors under dynamic hot-carrier stress. Unlike the monotonic decrease of maximum transconductance (G/sub m max/) in static stress, G/sub m max/ in dynamic stress is initially increased due to the channel shortening effect by holes injected into the gate oxide near the drain region and then decreased due to tail states generation at the gate oxide/channel interface and grain boundaries. The threshold voltage variations are dominated by two degradation mechanisms: (1) breaking of weak bonds and (2) breaking of strong bonds to obey the power-time dependence law with a slope of 0.4. The degradation of the sub-threshold slope is attributed to intra-grain bulk states generation. View full abstract»

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  • Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETs

    Page(s): 478 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB) |  | HTML iconHTML  

    Sensitive quantum-yield measurements (M) on n-channel MOSFETs for drain voltages (V/sub D/) near the bandgap voltage of silicon, showed an abnormal bell-shaped M versus gate voltage (V/sub G/) characteristic at 77 K. At higher V/sub D/, M decreases monotonously with increasing V/sub G/. Measured data is interpreted based on the general nature of electron energy distribution published by Monte-Carlo simulation groups and provide simultaneous experimental verification for the presence of a tail that depends strongly on lattice temperature and electron-electron interaction (EEI) broadening of the tail. Our data suggest EEI broadening of the tail even in the subthreshold regime. View full abstract»

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  • Improving the RF performance of 0.18 μm CMOS with deep n-well implantation

    Page(s): 481 - 483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (75 KB)  

    The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (FT) and maximum oscillation frequency (Fmax). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in FT and 25% increase in Fmax are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications. View full abstract»

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  • MOSFET drain/source charge partition under nonquasi-static switching

    Page(s): 484 - 486
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB) |  | HTML iconHTML  

    The channel charge partition of metal-oxide-semiconductor transistors in nonquasi-static switching has been studied. A new approach, with the help of a two-dimensional device simulator is used to separate the direct current and transient current component during device switching. Unlike the commonly accepted 40/60 drain/source channel charge partition ratio, our results show that it is closer to the 0/100 as long as the switch speed is higher than the channel charging time. The result is important for pass-gate type circuits to evaluate the amount of charge transferred to the source and drain nodes. View full abstract»

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  • Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

    Page(s): 487 - 489
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V/sub g/-VT=V/sub d/=1 V. The electrical gate oxide thickness in these devices is 21 /spl Aring/, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness. View full abstract»

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  • Electrical characterization of Al2O3 n-channel MOSFETs with aluminum gates

    Page(s): 490 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (59 KB)  

    High-effective mobilities are demonstrated in Al/sub 2/O/sub 3/ based n-channel MOSFETs with Al gates. The Al/sub 2/O/sub 3/ was grown in ultra-high vacuum using a reactive atomic beam deposition system. The mobility with maximum values at approximately 270 cm/sup 2//Vs, is found to approach that of SiO/sub 2/ based MOSFETs at higher fields. View full abstract»

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  • A new pad-oriented multiple-mode ESD protection structure and layout optimization

    Page(s): 493 - 495
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB) |  | HTML iconHTML  

    This work reports a new multiple-mode pad-oriented electrostatic discharge (ESD) protection structure, which protects input-output pads against ESD pulses of all modes. A unique pad-based quasi-symmetric layout design is devised to improve ESD robustness. The new ESD structure features tunable triggering voltage, low holding voltage, low on-impedance, low leakage (/spl sim/pA), fast response time (/spl sim/0.18 ns), and low parasitic effect. It can be placed under a bond pad and consumes little silicon. It passed 14 kV human body model and 15 kV air-gap International Electrotechnical Commission ESD zapping. It was demonstrated in commercial BiCMOS processes and is suitable for multiple-supply mixed-signal, parasitic-sensitive RF and high-pin-count ICs. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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