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IEEE Transactions on Computers

Issue 8 • Aug 1990

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Displaying Results 1 - 12 of 12
  • Analysis and design of CMOS Manchester adders with variable carry-skip

    Publication Year: 1990, Page(s):983 - 992
    Cited by:  Papers (46)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Two different CMOS implementations of the Manchester carry-skip adder are analyzed using the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, the authors develop efficient polynomial algorithms to determine near-optimal (in latency) as well as optimal block sizes for the one-level manchester adder with v... View full abstract»

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  • The set theory of arithmetic decomposition

    Publication Year: 1990, Page(s):993 - 1005
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    The set theory of arithmetic decomposition is a method of designing complex addition/subtraction circuits at any radix using strictly positional, sign-local number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation... View full abstract»

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  • Exact real computer arithmetic with continued fractions

    Publication Year: 1990, Page(s):1087 - 1105
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1232 KB)

    A representation of the computable real numbers by continued fractions is introduced. This representation deals with the subtle points of undecidable comparison and integer division, as well as representing the infinite 1/0 and undefined 0/0 numbers. Two general algorithms for performing arithmetic operations are introduced. The algebraic algorithm, which computes sums and products of continued fr... View full abstract»

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  • On-line CORDIC algorithms

    Publication Year: 1990, Page(s):1038 - 1052
    Cited by:  Papers (33)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB)

    A number of new algorithms to make an online CORDIC implementation are introduced. The online CORDIC algorithm takes n+6 clock cycles to compute a CORDIC function. It is estimated that an implementation of the proposed algorithm is six to seven times as fast as the traditional CORDIC approach for Given's rotation, and seven to eight times as fast for SVD computation View full abstract»

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  • Redundant logarithmic arithmetic

    Publication Year: 1990, Page(s):1077 - 1086
    Cited by:  Papers (40)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    A number system that offers advantages in some situations over conventional floating point and sign/logarithmic number systems is described. Redundant logarithmic arithmetic, like conventional logarithmic arithmetic, relies on table lookups to make the arithmetic unit simpler than an equivalent floating point unit. The cost of 32 bit subtraction in a redundant logarithmic number system is lower th... View full abstract»

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  • Evaluating elementary functions in a numerical coprocessor based on rational approximations

    Publication Year: 1990, Page(s):1030 - 1037
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    A different approach to hardware evaluation of elementary functions for high-precision floating-point numbers (in particular, the extended double precision format of the IEEE standard P754) is examined. The evaluation is based on rational approximations of the elementary functions, a method which is commonly used in scientific software packages. A hardware model is presented of a floating-point nu... View full abstract»

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  • A generalized multibit recoding of two's complement binary numbers and its proof with application in multiplier implementations

    Publication Year: 1990, Page(s):1006 - 1015
    Cited by:  Papers (56)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    A multibit recoding algorithm for signed two's complement binary numbers is presented and proved. In general, a k+1-bit recoding will result in a signed-digit (SD) representation of the binary number in radix 2k, using digits -2k-1 to +2k-1 including 0. It is shown that a correct SD representation of the original number is obtained by scanning K+1... View full abstract»

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  • An algorithm for redundant binary bit-pipelined rational arithmetic

    Publication Year: 1990, Page(s):1106 - 1115
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    The authors introduce a redundant binary representation of the rationals and an associated algorithm for computing the sum, difference, product, quotient, and other useful functions of two rational operands, using this representation. The algorithm extends R.W. Gosper's (1972) partial quotient arithmetic algorithm and allows the design of an online arithmetic unit with computations granularized at... View full abstract»

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  • An algorithm for scaling and single residue error correction in residue number systems

    Publication Year: 1990, Page(s):1053 - 1064
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB)

    An algorithm for scaling and single residue digit error correction is proposed. This algorithm is fully based on mixed radix conversion (MRC). The redundant digits of MRC can be used to establish a lookup table to correct single residue digit errors. By using this algorithm the error correction and scaling operation can be unified in one hardware, thereby reducing the complexity of these implement... View full abstract»

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  • Radix-4 square rot without initial PLA

    Publication Year: 1990, Page(s):1016 - 1024
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    A systematic derivation of a radix-4 square-root algorithm using redundant residual and result is presented. Unlike other similar schemes it does not use a table lookup or PLA for the initial step, resulting in a simpler implementation without any time penalty. The scheme can be integrated with division and incorporates an on-the-fly conversion and rounding of the result, thus eliminating a carry-... View full abstract»

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  • On modulus replication for residue arithmetic computations of complex inner products

    Publication Year: 1990, Page(s):1065 - 1076
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    A technique is presented for coding weighted magnitude components (e.g. bits) of numbers directly into polynomial residue rings, such that repeated use may be made of the same set of moduli to effectively increase the dynamic range of the computation. This effectively limits the requirement for large sets of relatively prime moduli, For practical computations over quadratic residue rings, at least... View full abstract»

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  • Square rooting algorithms for integer and floating-point numbers

    Publication Year: 1990, Page(s):1025 - 1029
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org