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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct 2001

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Displaying Results 1 - 25 of 42
  • Intrinsic MOSFET capacitance coefficients

    Page(s): 2384 - 2393
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    Intrinsic capacitance coefficients are derived for metal oxide semiconductor field effect (MOSFET) based on the inversion charge relation. A simple expression is obtained for the channel charge as a function of distance. Integrals for the proportionately partitioned source and drain-stored charges are obtained analytically. The resulting expressions are valid from deep subthreshold to strong inversion. A saturation charge qmda is introduced that allows handling of short-channel effects. The capacitance coefficients have the required source/drain symmetry View full abstract»

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  • Investigation of defects in deposited oxides with a frequency resolved capacitance technique

    Page(s): 2342 - 2347
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    In this paper we propose a new tool to investigate defective oxides. The technique measures the differential capacitance of MOS devices under substrate accumulation as a function of the small-signal frequency. In off-stochiometric oxides deposited by plasma-enhanced CVD we measure a consistent increase of capacitance while decreasing frequency. An analytical model of capacitance is developed, starting from the hypothesis that trapped charge hops between defect sites around the Fermi level via a phonon-assisted mechanism. The hopping characteristic time depends on the energy difference and distance between defects and is compared with the inverse frequency. This gives rise to the observed dispersive behavior of the capacitance. Experimental results are successfully reproduced by the proposed model. Defect densities up to 1020 cm-3 were extracted, with an energy span as low as 0.1 eV and hopping distance around 25 Å View full abstract»

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  • Molecular beam epitaxy growth of TmP/GaAs and transistor action in GaP/TmP/GaAs heterostructures

    Page(s): 2205 - 2209
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    The growth of thulium phosphide (TmP) by molecular beam epitaxy (MBE) on GaAs substrate is reported. Good epilayer quality was demonstrated through X-ray diffraction (XRD), atomic force microscopy (AFM) and transmission electron microscopy (TEM) analysis. The closely lattice matched TmP layer was n-type with an electron concentration of 1.6×1021 cm-3 and a room temperature mobility of 4.8 cm2V-1s-1. The Schottky barrier height determined from 1/capacitance2 (1/C2) versus voltage (V) measurements is about 0.81 eV which agrees well with the value obtained through the current-voltage (I-V) measurements. In this work, we also report transistor action in a GaP/TmP/GaAs structure, for which chemical bonding techniques were employed. From I-V measurements, a common base current gain α≈0.55 at VCB=0 was obtained at room temperature View full abstract»

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  • Modeling of oxidation-induced strain and its effect on the electronic properties of Si waveguides

    Page(s): 2405 - 2409
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB) |  | HTML iconHTML  

    We have studied the influence of oxidation-induced strain on the electronic structure in Si quantum wires and quantum point contacts. The strain calculations were done using a semiempirical approximation which enabled three-dimensional (3-D) strain simulations of the device structures. The strain-induced deformation of the conduction band gives rise to a 3-D potential minimum having a depth of ~35 meV. In addition to the formation of localized electron states in the channel, our calculations predict crossing of transverse energy levels corresponding to different conduction band minima. Our calculations also predict strain-induced channeling of electrons to the edges of the structure View full abstract»

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  • Physical modeling of the reverse-short-channel effect for circuit simulation

    Page(s): 2449 - 2452
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    The proposed threshold-voltage (Vth) model for circuit simulation includes reverse-short-channel effects (RSCE) and short-channel effects (SCE) based on their respective physical origins. A linear vertical-impurity profile approximation for simplified RSCE-modeling already enables 8 mV average Vth-accuracy (max<45 mV) under all bias conditions for source, drain, and bulk for Lgate down to 0.15 μm. The complete Vth-model needs only ten constant Lgate-independent parameters View full abstract»

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  • Optimum halo structure for sub-0.1 μm CMOSFETs

    Page(s): 2357 - 2362
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    Optimized halo structures for sub-0.1 μm CMOSFETs are evaluated. Halo profiling using indium implantation for nMOSFETs is investigated over a wide range of implantation dosages and energies. Performance degradation due to interstitial Si resulting from In-halo implantation can be reduced using thermal annealing at medium temperatures for longer periods of time. Lower-temperature composite liner-oxide/SiN-spacer technology is proposed for pMOSFETs to suppress device performance degradation. Optimized halo structures using indium for nMOSFETs and arsenic for pMOSFETs to obtain high-performance sub-0.1 μm CMOSFETs are proposed View full abstract»

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  • Back-gate and series resistance effects in LDMOSFETs on SOI

    Page(s): 2410 - 2416
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    Detailed experimental results are used to develop a new model for the linear region of operation of lateral DMOSFETs (LDMOSFETs) on silicon-on-insulator (SOI) that includes the influence of the buried oxide and back-gate. Back-gate biasing results in double-channel conduction and bias-dependent series resistance. Pertinent techniques for parameter extraction are presented and contrasted to those currently used in low-voltage SOI MOSFETs. The typical feature of LDMOSFETs is the significant change in series resistance as the back-gate is driven from accumulation to inversion. The model allows a clear identification of the architectural and technological parameters of the device View full abstract»

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  • Local iterative Monte Carlo analysis of electron-electron interaction in short-channel Si-MOSFETs

    Page(s): 2323 - 2330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    The effects of electron-electron interaction on the electron distribution, substrate current, and gate current in short n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied using the local iterative Monte Carlo (LIMC) approach. The complete distribution function is always available at each step of this approach and with reduced noise with respect to standard Monte Carlo (MC) simulation. Therefore, electron-electron interaction can be evaluated efficiently using scattering rates, allowing one to examine hot carrier effects that may play an important role for device reliability and characterization. Results for MOSFETs with channel length as short as 25 nm show that electron-electron interaction leads to an increase of the high energy tail of the electron distributions at the transition from channel to drain. The electron density around 3 eV is significantly increased even if the applied voltage is in the 1.0 V range View full abstract»

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  • Physics and applications of the Schottky junction transistor

    Page(s): 2421 - 2427
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    This paper presents the results from numerical simulations of a novel subthreshold transistor configuration. The device uses the input current from a forward-biased Schottky gate to control the larger current flowing in a depleted channel. Analytical approximations are used to derive the current gain of the transistor. The numerical simulations confirm the analytical derivation and show that a 0.5 μm gate length device would have a cutoff frequency approaching 10 GHz for supply voltages less than 0.5 V. Possible applications of the device in the areas of micropower analog circuits and ULSI logic are discussed View full abstract»

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  • Group IVB metal oxides high permittivity gate insulators deposited from anhydrous metal nitrates

    Page(s): 2348 - 2356
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    The electrical performance of column IVB metal oxide thin films deposited from their respective anhydrous metal nitrate precursors show significant differences. Titanium dioxide has a high permittivity, but shows a large positive fixed charge and low inversion layer mobility. The amorphous interfacial layer is compositionally graded and contains a high concentration of Si-Ti bonds. In contrast, ZrO2 and HfO 2 form well defined oxynitride interfacial layers and a good interface with silicon with much less fixed charge. The electron inversion layer mobility for an HfO2/SiOxNy /Si stack appears comparable to that of a conventional SiO2 /Si interface View full abstract»

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  • Impact of a high electric field on the extraction of the generation lifetime from the reverse generation current component of shallow n+-p-well diodes

    Page(s): 2445 - 2446
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB) |  | HTML iconHTML  

    A procedure is proposed to extract the thermal generation lifetime (τg) profile in the depletion region of shallow n+ -p-well junctions surrounded by shallow trench isolation from the generation current density. This is achieved by taking account of the electric field enhancement factor. As will be shown, a more realistic τg profile is obtained that better reflects the trap density profile, corresponding with the deep boron ion implantation-related extended defects View full abstract»

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  • Reliability of low temperature poly-silicon TFTs under inverter operation

    Page(s): 2370 - 2374
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    We have studied the reliability of low-temperature polycrystalline-silicon thin-film-transistors (TFTs) under dynamic bias stress using a CMOS inverter circuit. A remarkable decrease in the mobility and the ON-current was observed in n-channel TFTs under dynamic stress. The degradation depends strongly on the falling edge of the voltage pulse and the number of pulses. Observation by emission microscopy revealed that hot electrons were generated around the edge of the drain region in the n-channel TFT. We also confirmed that TFTs with lightly doped drain were less degraded. Based on these experimental results, a new degradation model was proposed. The model suggests that upon the gate voltage drop, electrons move rapidly to the drain, thus, becoming hot and creating electron traps in the grain boundaries around the drain. Consequently, the ON-current is decreased View full abstract»

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  • Lateral profiling of interface traps and oxide charge in MOSFET devices: charge pumping versus DCIV

    Page(s): 2303 - 2309
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    An improved oxide-charge and interface-trap lateral profiling charge pumping technique (iLPCP) is described. Erase-induced oxide charge and interface traps are investigated in flash EPROM devices. It is shown that the improved technique allows the extraction of profiles in cases where the previous method does not yield satisfactory results. A comparative study of iLPCP and of an existing direct current (DCIV) technique for lateral profiling of interface traps is conducted: both erase- and program-induced interface traps are investigated in flash EPROM devices. The results indicate that 1) iLPCP probes a much bigger portion of the gate region; 2) iLPCP probes a wider energy range; 3) DCIV is more sensitive deep in the channel and thus complements iLPCP View full abstract»

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  • Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism

    Page(s): 2317 - 2322
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density Nt, and the trap energy level Et. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10-13 s and Et of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well View full abstract»

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  • Modeling of electron transport and luminance in SrS:Cu,Ag ACTFEL display devices

    Page(s): 2242 - 2248
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    Transient and steady state responses of luminance and current in SrS:Cu,Ag ac thin film electroluminescent (ACTPEL) display devices were measured and analyzed. The results indicated the importance of bulk space charge, which was attributed to ionized activators in the bulk phosphor layer. For dented voltage pulse excitation, four luminance peaks were observed. These were labeled as the leading edge (LE) peak, dent peak, beginning of trailing edge (BTE) peak and the middle of trailing edge (MTE) peak. Ionized activators play an important role not only in affecting the net phosphor field but also in the device luminance during the trailing as well as the leading edges of the voltage pulse. It is shown that the dent peak and the BTE are due to a bulk recombination process instead of the backflow from the anodic interface. The luminance behavior of the device can be understood in terms of the bulk dipoles in the phosphor layer. A bulk dipole consists of a positively charged ionized Cu activator and a “daughter” trap (negatively charged) in its vicinity. A physical model for various optoelectronic processes is presented. The model can explain experimental data in a qualitative fashion View full abstract»

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  • Design and performance of a vertical cavity surface emitting laser based on III-V quaternary semiconductor alloys for operation at 1.55 μm

    Page(s): 2228 - 2237
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    A highly efficient Vertical Cavity Surface Emitting Laser (VCSEL) has been designed and fabricated for operation at a wavelength of 1.546 μm. The device design incorporates optimized Bragg mirrors with minimized number of periods. The present structure employs quaternary III-V semiconductor alloys with GaInAsP as the active layer and AlGaInAs/InP multilayer stack as the Distributed Bragg Reflector (DBR). The material parameters of the quaternary alloys including index of refraction and bandgap energy are calculated over the entire composition range. The difference in the indices of refraction between AlGaInAs and InP alternating layers is found to be 0.46 resulting in a significant reduction of the number of DBR layers. The MBE technique is employed for the epitaxial VCSEL structure growth and the selective oxidation of AlInAsP single layer is used to form the current confinement aperture. The VCSEL gain performance has been calculated and measured, resulting in the experimental threshold current of about 3 mA and the output power of 1 mW View full abstract»

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  • Analysis of a technology for CZ bifacial solar cells

    Page(s): 2337 - 2341
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    A bifacial cell technology for Cz Si and evaporated contacts is presented. A p+nn+ structure on high resistivity material gives 17.7% for n+ side illumination and 15.2% for p + side illumination. Cell performance is analyzed by fitting experimental measurements with PC1D. Analysis shows that p+ layer puts a limit to cell performance, mainly due to a high surface recombination velocity. The boron depleted zone near the surface also enhances recombination, but its effect can be reduced by performing a boron etch-back step in the process. Cells with boron etch-back give higher short-circuit current and a reduction of open-circuit voltage of around 10 mV. These results are consistent with the PC1D model View full abstract»

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  • Study of low-frequency excess noise in GaN thin films deposited by RF-MBE on intermediate-temperature buffer layers

    Page(s): 2400 - 2404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    Low-frequency excess noise was measured in a series of GaN epitaxial films deposited by RF-plasma assisted molecular beam epitaxy (MBE). The GaN epitaxial layers were grown on double buffer layers, each consisting of an intermediate-temperature buffer layer (ITBL) deposited at 690°C and a conventional low-temperature buffer layer grown at 500°C. The Hooge parameters for the as-grown films were found to depend on the thickness of ITBL with a minimum value of 7.34×10 -2 for an optimal ITBL thickness of 800 nm. The observed improvements in the noise properties are attributed to the relaxation of residual strain within the material, leading to a corresponding reduction in crystalline defects View full abstract»

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  • DC and microwave noise transient behavior of InP/InGaAs double heterojunction bipolar transistor (DHBT) with polyimide passivation

    Page(s): 2192 - 2197
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    DC and microwave noise transient behavior of InP/InGaAs double heterojunction bipolar transistor (DHBT) with polyimide passivation is reported in this paper for the first time. The base transient current is believed to be due to the change of surface potential near the base-emitter junction perimeter at the polyimide/emitter interface resulting from a decrease in the amount of trapped electrons in the polyimide. We also find that the surface potential on the sidewall of collector-emitter affected by the charge trapping and detrapping in polyimide may induce a parasitic polyimide field effect transistor along the surface of the base-collector junction which results in an excess collector transient current. These base and collector current transients result in associated transient of broadband shot noise. The time dependence of microwave noise figures due to the excess transients is also investigated. The better understanding of the mechanisms of the noise transient behavior of the InP HBT device is very useful to improve the device and circuit reliability View full abstract»

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  • Partial filling of a quantum dot intermediate band for solar cells

    Page(s): 2394 - 2399
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    This paper describes how to partially fill the intermediate band formed by the confined states of quantum dots with electrons. Efficiencies of up to 63.2% have been calculated in ideal cases for solar cells with this intermediate band. In order to achieve this, the barrier region is n-doped so that the electrons delivered by the donors fall into the otherwise empty intermediate band states. This method produces a fully space-charged structure whose electrostatic properties are studied in this paper, thus confirming the feasibility of the proposed method. Partial filling of the intermediate band is necessary to provide strong absorption in transitions from it to both the valence and the conduction bands View full abstract»

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  • A study on the new type sustaining electrode showing high luminous efficiency in AC PDPs

    Page(s): 2255 - 2259
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    In order to improve the luminous efficiency of ac plasma display panel (PDP), a new bridge type sustaining electrode is suggested. The luminous efficiency of the ac PDP with suggested new sustaining electrodes is improved about 30% compared with that of conventional sustaining electrodes. Furthermore, the suggested ac PDP is maintained almost the same luminance with the conventional ones, and this type has a merit of free alignment between front and rear panels View full abstract»

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  • High-sensitivity and no-crosstalk pixel technology for embedded CMOS image sensor

    Page(s): 2221 - 2227
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A high-photosensitivity and no-crosstalk pixel technology has been developed for an embedded active-pixel CMOS image sensor, by using a 0.35-μm CMOS logic process. To increase the photosensitivity, we developed a deep p-well photodiode and an antireflective film, consisting of Si3N4 film, for the photodiode surface. To eliminate the high voltage required for the reset transistor in the pixel, we used a depletion-type transistor as the reset transistor. The reset transistor also operates as an overflow control gate, which enables antiblooming overflow when excess charge is generated in the photodiode by high-illumination conditions. To suppress pixel crosstalk caused by obliquely incident light, a double-metal photoshield was used, while crosstalk caused by electron diffusion in the substrate was suppressed by using the deep p-well photodiode. A 1/3-in 330-k-pixel active-pixel CMOS image sensor was fabricated using this technology. A sensitivity improvement of 110% for 550-nm incident light was obtained by using the deep p-well photodiode, while an improvement of 24% was obtained by using the antireflective film. The pixel crosstalk was suppressed to less than 1% throughout the range of visible light View full abstract»

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  • A SOI LDMOS technology compatible with CMOS, BJT, and passive components for fully-integrated RF power amplifiers

    Page(s): 2428 - 2433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    This paper presents a silicon-on-insulator (SOI) lateral double-diffused MOS transistor (LDMOS) technology, which is compatible with complementary metal oxide semiconductor (CMOS), lateral bipolar junction transistor (BJT), and passive components for the implementation of radio frequency (RF) fully-integrated power amplifiers (IPAs) used in wireless communications. This technology allows complete integration of the low-cost and low-power front-end circuits with the baseband circuits for single-chip wireless communication systems. The SOI LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 4.5 GHz fT , and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length 0.8/-1.2 V threshold voltage), lateral BJT (18 V BVCBO, and 6.4 V BVCEO) and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz for an inductance of 7 nH) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation. A fully functional high performance integrated power amplifier for 900 MHz wireless communication transceivers is also demonstrated View full abstract»

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  • A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film

    Page(s): 2363 - 2369
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    A novel dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film is described. It is based on a new finding that threshold voltage (Vth) depends on the concentration of nitrogen in the TiNx gate electrode. We found that a V th shift as high as -110 mV is controlled by low-energy nitrogen-ion implantation (N I/I) into the titanium nitride film. By using this technology only for nMOSFETs, dual-metal gate CMOS devices are fabricated with a CMOS-process compatibility. A low Vth is achieved for both n- and pMOSFETs by combining N I/I and a low-doped channel structure View full abstract»

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  • Strained-Si on Si1-xGex MOSFET inversion layer centroid modeling

    Page(s): 2447 - 2449
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    An accurate model for the inversion charge centroid of strained-Si on Si1-xGex metal-oxide semiconductor field effect transistors (MOSFETs) has been developed including the dependencies on the germanium mole fraction, the doping concentration, and the width of the strained-Si layer. We have also obtained a good estimation of the inversion charge. The inclusion of quantum effects in classical simulators by means of a corrected gate-oxide width can be easily performed making use of this new model View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology