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Computer

Issue 7 • Date July 1990

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Displaying Results 1 - 11 of 11
  • Comments, with reply, on 'A noninvasive architecture to monitor real-time distributed systems', by J. Tsai et al

    Publication Year: 1990, Page(s):12 - 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB)

    The commenter maintains that the above-titled article (see ibid., vol.23, no.3, p.22-3, 1990) on unobtrusive real-time system monitoring fails to demonstrate much appreciation for the software side and as a result provides a somewhat misleading view of the state of the art in real-time system monitoring. He states that the article fails to mention that modern real-time application software written... View full abstract»

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  • Correction to 'Directory-based cache coherence in large-scale multiprocessor'

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (71 KB)

    A corrected version of fig. 4 of the above-titled paper (see ibid., vol.23, no.6, p.49-58, 1990) is provided. Because two shades of black appeared to be continuous when printed, the speech bar chart in the figure did not properly illustrate the difference between the 'Read only processing by block' and the 'Unoptimized trace' portions of the bars.<> View full abstract»

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  • Fault-tolerant systems

    Publication Year: 1990, Page(s):15 - 17
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (637 KB)

    Two mishaps early this year forcefully reminded the authors how important computer systems' reliability has become to human well-being in this last decade of the 20th century. In January, large parts of AT&T's long-distance telephone switching networks failed because of a software problem. Then, in February, a 'fly by wire' Airbus A320 aircraft crashed in Bangalore, India. While a definitive cause... View full abstract»

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  • Fault-tolerant computing: fundamental concepts

    Publication Year: 1990, Page(s):19 - 25
    Cited by:  Papers (64)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (722 KB)

    The basic concepts of fault-tolerant computing are reviewed, focusing on hardware. Failures, faults, and errors in digital systems are examined, and measures of dependability, which dictate and evaluate fault-tolerance strategies for different classes of applications, are defined. The elements of fault-tolerance strategies are identified, and various strategies are reviewed. They are: error detect... View full abstract»

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  • Fault tolerance in commercial computers

    Publication Year: 1990, Page(s):26 - 37
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (971 KB)

    A taxonomy of fault tolerance in commercial computers is set forth. It is organized around three orthogonal axes: the sources of errors the computer tolerates, the computer's approach to tolerating errors, and the computer's structure. Each of these is briefly discussed. An example of each class in the taxonomy is presented, as well as its approach to answering the following questions: (1) Is the ... View full abstract»

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  • Definition and analysis of hardware- and software-fault-tolerant architectures

    Publication Year: 1990, Page(s):39 - 51
    Cited by:  Papers (90)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1202 KB)

    A structured definition of hardware- and software-fault-tolerant architectures is presented. Software-fault-tolerance methods are discussed, resulting in definitions for soft and solid faults. A soft software fault has a negligible likelihood or recurrence and is recoverable, whereas a solid software fault is recurrent under normal operations or cannot be recovered. A set of hardware- and software... View full abstract»

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  • Reliability estimation of fault-tolerant systems: tools and techniques

    Publication Year: 1990, Page(s):52 - 61
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (911 KB)

    A comparative evaluation of state-of-the-art tools and techniques for estimating the reliability of fault-tolerant computing systems is presented. The theory of reliability estimation is briefly reviewed. Five current approaches are compared in detail: HARP (hybrid automated reliability predictor), SURE (semi-Markov unreliability range estimator), HEIRESS (hierarchical estimation of interval relia... View full abstract»

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  • Error-control coding in computers

    Publication Year: 1990, Page(s):63 - 72
    Cited by:  Papers (34)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (829 KB)

    In this article, intended for readers with basic knowledge in coding, the codes used in actual systems are surveyed. Error control in high-speed memories is examined, including bit-error-correcting/detecting codes, byte-error-correcting/detecting codes, and codes to detect single-byte errors as well as correct single-bit errors and detect double-bit errors. Tape and disk memory codes for error con... View full abstract»

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  • Fault tolerance in VLSI circuits

    Publication Year: 1990, Page(s):73 - 83
    Cited by:  Papers (49)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1093 KB)

    The defects that can occur when manufacturing VLSI ICs and the faults that can result are described. Some commonly used restructuring techniques for avoiding defective components are discussed. Several defect-tolerant designs of memory ICs, logic ICs, and wafer-scale circuits are presented. Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of red... View full abstract»

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  • Design techniques for testable embedded error checkers

    Publication Year: 1990, Page(s):84 - 88
    Cited by:  Papers (14)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability.<> View full abstract»

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  • Standards-the history of Posix: a study in the standards process

    Publication Year: 1990, Page(s):89 - 92
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    The background of the Posix (an acronym for the standard formally known as Portable Operating System Interface for Computer Environments) standardization is described. Significant steps and/or stages in the process are discussed. They include setting up key guidelines; a methodology for identifying consensus that had evolved from software engineering groups writing the rationale; expanding partici... View full abstract»

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Aims & Scope

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed articles written for and by computer researchers and practitioners representing the full spectrum of computing and information technology, from hardware to software and from emerging research to new applications. 

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Editor-in-Chief
Sumi Helal
University of Florida
sumi.helal@gmail.com