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IEEE Micro

Issue 4 • Date July-Aug. 2001

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Displaying Results 1 - 10 of 10
  • An earful about Zvi's e-mail

    Publication Year: 2001, Page(s):8 - 10
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    Freely Available from IEEE
  • The challenges of wearable computing: Part 1

    Publication Year: 2001, Page(s):44 - 52
    Cited by:  Papers (50)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Wearable computing pursues an interface ideal of a continuously worn, intelligent assistant that augments memory, intellect, creativity, communication, and physical senses and abilities. Many challenges await wearable designers as they balance innovative interfaces, power requirements, network resources, and privacy concerns. This survey describes the possibilities offered by wearable systems and,... View full abstract»

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  • Java use in mobile information devices: Introducing JTRON

    Publication Year: 2001, Page(s):16 - 21
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    Using Java, next-generation mobile devices can serve as highly functionally distributed systems. The JTRON specification achieves real-time performance in Java-based mobile systems View full abstract»

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  • A java-enabled evolution

    Publication Year: 2001, Page(s):2 - 3
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    First Page of the Article
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  • Making it work

    Publication Year: 2001, Page(s):70 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

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  • Cached DRAM for ILP processor memory access latency reduction

    Publication Year: 2001, Page(s):22 - 32
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors View full abstract»

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  • More standardization skullduggery

    Publication Year: 2001, Page(s):12 - 15, 69
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    As a follow-up to the May/June Micro Law column on abuse of the standard-setting process, I now turn to Rambus' version of the previously summarized Secret Squirrel saga. A jury in Richmond, Virginia, found that with the aid of a secret informant (designated Secret Squirrel) inside the Joint Electronic Devices Engineering Council (JEDEC) standard-setting group, Rambus engaged in industrial-grade s... View full abstract»

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  • The challenges of wearable computing: Part 2

    Publication Year: 2001, Page(s):54 - 67
    Cited by:  Papers (16)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB) | HTML iconHTML

    For pt. 1 see ibid. Wearable computing pursues an interface ideal of a continuously worn, intelligent assistant that augments memory, intellect, creativity, communication, and physical senses and abilities. Many challenges await wearable designers. Part 2 begins with the challenges of network resources and privacy concerns. This survey describes the possibilities offered by wearable systems and, i... View full abstract»

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  • Why standards are here to stay

    Publication Year: 2001, Page(s):6 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

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  • Data cache and direct memory access in programming mediaprocessors

    Publication Year: 2001, Page(s):33 - 42
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    Mediaprocessors provide high performance by using both instruction- and data-level parallelism. Because of the increased computing power, transferring data between off- and on-chip memories without slowing down the core processor's performance is challenging. Two methods, data cache and direct memory access, address this problem in different ways View full abstract»

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IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center