Issue 9 • Date Sep 2001
Filter Results
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On the complexity of gate duplication
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PDF (156 KB)
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Boolean matching for LUT-based logic blocks with applications to architecture evaluation and technology mapping
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PDF (352 KB)
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Synthesis of power-managed sequential components based on computational kernel extraction
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PDF (296 KB)
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Switching activity generation with automated BIST synthesis for performance testing of interconnects
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PDF (308 KB)
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Concurrent test for digital linear systems
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PDF (204 KB)
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Theory of latency-insensitive design
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PDF (496 KB)
Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu


