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IEEE Design & Test of Computers

Issue 3 • June 1990

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Displaying Results 1 - 5 of 5
  • A minimalist approach to VHDL logic modeling

    Publication Year: 1990, Page(s):12 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (848 KB)

    The VHDL Design Exchange Group (VDEG), which consists of VHDL (VHSIC hardware description language) suppliers and users, was formed to promote the identical operation of VHDL models on different tools. One task of VDEG, which is still ongoing, is to develop a consensus logic model and a method for its use. VDEG and the VDEG's work on this task as of September 1989 are described. The definition of ... View full abstract»

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  • A VHDL standard package for logic modeling

    Publication Year: 1990, Page(s):25 - 32
    Cited by:  Papers (3)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (619 KB)

    A package facility that enables designers to write models intuitively, without being forced to work with the underlying complexity and verboseness of the base VHDL (VHSIC hardware description language), is described. The VHDL environment handles all technology-dependent calculations automatically and drops in the lookup tables and utility function code as appropriate. In addition, the VHDL package... View full abstract»

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  • A value system for switch-level modeling

    Publication Year: 1990, Page(s):33 - 41
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB)

    An approach to switch modeling that provides an excellent compromise between accuracy and performance and requires only minor modifications to basic gate-level simulators is described. The evaluation technique is fully compatible with the VHDL (VHSIC hardware description language) specification. Switch and node models are implemented as primitive elements to achieve maximum performance, but models... View full abstract»

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  • Transparent logic modeling in VHDL

    Publication Year: 1990, Page(s):42 - 48
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (478 KB)

    Modeling conventions and VHDL (VHSIC hardware description language) library techniques for transparently mapping between multivalued logic systems without modifying the model itself is described. Using these conventions and the VHDL library system, designers can choose any logic system compatible with the models and use if for simulation. Also described are some of the requirements the multivalued... View full abstract»

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  • Logic modeling in WAVES

    Publication Year: 1990, Page(s):49 - 55
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    WAVES, which stands for waveform and vector exchange specification, is a way to represent in text the histories of logic signals and the requirements placed on them. It is intended to serve as a way of exchanging information between simulator and tester environments. A description is given of the WAVES event-value concept, which captures both the logic value sets used in simulation and the pin cod... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty