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Electron Devices, IEEE Transactions on

Issue 9 • Date Sept. 2001

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Displaying Results 1 - 25 of 49
  • Changes in the Editorial Board

    Publication Year: 2001 , Page(s): 1843
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    Freely Available from IEEE
  • Theoretical study of RF-breakdown in bulk GaN and GaN MESFETs

    Publication Year: 2001 , Page(s): 1844 - 1849
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (89 KB) |  | HTML iconHTML  

    RF-breakdown was studied in bulk GaN and in GaN MESFETs using a full band Monte Carlo simulator. It was found that in bulk materials, increasing the frequency of an applied RF field would result in a lower overall impact ionization rate and consequently lead to higher breakdown fields. It was also found that the RF-breakdown voltage of devices increases with increasing frequency of the applied large signal RF excitation. The frequency dependence of RF-breakdown and the difference between RF and dc-breakdown is explained based on the time response of the particle energy to the change in the applied RF excitation View full abstract»

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  • Dependence of the current and power efficiencies of organic light-emitting diode on the thickness of the constituent organic layers

    Publication Year: 2001 , Page(s): 2131 - 2137
    Cited by:  Papers (34)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    The dependence of the current and power efficiencies of bi-layer organic light-emitting diodes (OLEDs) on the thickness of the constituent organic layers is reported. The thickness of the electron and hole transport layers was simultaneously varied to determine the optimal configuration for power efficiency. It was verified that the inclusion of a suitable electrode buffer layer reduced the effective energy barrier against carrier injection, thus improved the injection efficiency. An optimal thickness for the electrode buffer layer was also identified and explained View full abstract»

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  • Electric-field-related reliability of AlGaAs/GaAs power HFETs: bias dependence and correlation with breakdown

    Publication Year: 2001 , Page(s): 1929 - 1937
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    This work shows experimental and simulated data of hot electron degradation of power AlGaAs/GaAs HFETs with different gate lengths and recess widths, and uses them to infer general indications on the bias and geometry dependence of the device high-field degradation, the meaningfulness of the breakdown voltage figure of merit from a reliability standpoint, and the physical phenomena taking place in the devices during the stress and leading to performance degradation. Possible formulations of a voltage-acceleration law for lifetime extrapolation are also tested View full abstract»

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  • Hole and electron mobility enhancement in strained SiGe vertical MOSFETs

    Publication Year: 2001 , Page(s): 1975 - 1980
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions View full abstract»

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  • Offset in CMOS magnetotransistors. I. Analysis of causes

    Publication Year: 2001 , Page(s): 1945 - 1953
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    Fabrication imperfections cause offset in CMOS magnetotransistors (MTs). In this paper, MT offset is experimentally characterized and its causes are analyzed for two different commercial CMOS processes. For the MT structures chosen as references, the average absolute value of the offset in terms of a relative imbalance of two collector currents is up to 2.7%. The mean offset temperature drift between -40°C and +140°C is 0.25%. The offset exhibits a high degree of variation on a very small spatial scale. Additionally, variations on a large scale over the wafer are observed and, in some cases, systematic influences. The actual offset contributions of the various identified possible sources are investigated. Misalignment of the metal contact mask occurring during photolithography dominates large scale offset variations and can also have a systematic component. Another systematic influence arises from nonorthogonal dopant implantation. Doping inhomogeneities are a dominating contribution to local variations as indirect evidence suggests. Further, mismatch in emitter-collector spacing is critical. Suppressed sidewall injection magnetotransistors (SSIMTs) showing an enhanced sensitivity exhibit a quadrupling of the offset, which comes from a misalignment of the emitter guard ring. The obtained results are the basis for dedicated offset reduction in MTs as well as the development of MT-like test structures for processing tolerances View full abstract»

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  • Hydrogen-sensitive characteristics of a novel Pd/InP MOS Schottky diode hydrogen sensor

    Publication Year: 2001 , Page(s): 1938 - 1944
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    Steady-state and transient hydrogen-sensing characteristics of a novel Pd/InP metal-oxide-semiconductor (MOS) Schottky diode under atmospheric conditions are presented and studied. In presence of oxide layer, the significant increase of barrier height improves the hydrogen sensitivity even at lower operating temperatures. Even at a very low hydrogen concentration environment, e.g., 15 ppm H2 in air, a significant response is obtained. Two effects, i.e., the removal of Fermi-level pinning caused by the donor level in the oxide and the reduction of Pd metal work function dominate the hydrogen sensing mechanism. Furthermore, the reaction kinetics incorporating the water formation upon hydrogen adsorption is investigated. The initial heat of adsorption for the Pd/oxide interface is estimated to be 0.42 eV/hydrogen atom. The coverage dependent heat of adsorption plays an important role in hydrogen response under steady-state conditions. In accordance with the Temkin isotherm behavior, the theoretical prediction of interface coverage agrees well with the experimental results over more than three decades of hydrogen partial pressure View full abstract»

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  • A study of the threshold voltage variation for ultra-small bulk and SOI CMOS

    Publication Year: 2001 , Page(s): 1995 - 2001
    Cited by:  Papers (39)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB) |  | HTML iconHTML  

    This paper addresses the scalability of bulk CMOS, and the feasibility of intrinsic channel SOI (IC-SOI) CMOS, as an alternative to the bulk, in view of the threshold voltage (VTH) fluctuations. The impact of dopant-induced VTH variations on bulk CMOS SRAM operation is evaluated using a newly proposed analytical method. It is estimated that the bulk SRAM performance will be seriously degraded as the channel length approaches 25-30 nm even if an elaborate redundancy scheme is used. For the IC-SOI FETs, instead of the dopant fluctuations, silicon thickness variation is a critical issue. However, systematic simulation results show that, by optimizing the FET design, the thickness-induced VTH variations for both planar single gate and vertical double gate 25 mm IC-SOI FETs will be acceptable, assuming a reasonable thickness deviation range. Therefore, the IC-SOI CMOS is expected to be superior to the bulk counterpart at L=25 nm. It was also found that optimizing the back bias is necessary for suppressing the VTH variations of the single gate IC-SOI FETs View full abstract»

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  • Offset in CMOS magnetotransistors. II. Reduction

    Publication Year: 2001 , Page(s): 1954 - 1960
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    For pt.I see ibid., vol.48, no.9, pp.1945-53 (2001). Offset reduction principles for complementary metal oxide semiconductor (CMOS) magnetotransistors (MTs) are discussed and several approaches are examined experimentally. Special emphasis is put on addressing the MT offset causes previously identified as most critical. Contributions from metal contact misalignment are suppressed by an improved emitter shape and metal contact position as well as by enhanced process control. Implantation angle effects are avoided by an orthogonal implant or are corrected for with the knowledge of the actual implant direction. Small scale effects from, for example, doping inhomogeneities or emitter-collector spacing mismatch are averaged out along an increased device edge length or in arrays of MTs. Emitter guard misalignment in suppressed-sidewall-injection-MTs (SSIMTs) is avoided by self-aligning the guard with poly-silicon mashing, MTs with average absolute values of offset below 0.14% between -40°C and +140°C are achieved. These offsets are equivalent to a magnetic induction below 4 mT at room temperature View full abstract»

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  • Basic feasibility constraints for multilevel CHE-programmed flash memories

    Publication Year: 2001 , Page(s): 2032 - 2042
    Cited by:  Papers (11)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This paper discusses the basic constraints for the feasibility of multilevel (ML) Flash memories, with specific reference to devices programmed by channel hot electron injection. Issues such as programming algorithm, program and read disturb immunity, data retention, and sense circuitry sensitivity are considered. Experimental data concerning the most suited programming algorithm and reliability aspects are given. A guideline for the evaluation of ML storage feasibility is provided, and a simple set of equations for basic constraint estimation is derived View full abstract»

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  • Memory operations of 1T2C-type ferroelectric memory cell with excellent data retention characteristics

    Publication Year: 2001 , Page(s): 2002 - 2008
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (171 KB) |  | HTML iconHTML  

    A novel FET-type ferroelectric memory cell with one-transistor, and two-capacitor (1T2C) structure was fabricated and characterized, in which the generation of depolarization field in ferroelectric film during data retention was suppressed by polarizing two ferroelectric capacitors in opposite directions. It was demonstrated that the stored data were nondestructively read-out and their retention time was much longer than that of conventional ferroelectric-gate FET View full abstract»

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  • Observations of backgate impedance dispersion in GaAs isolation structures

    Publication Year: 2001 , Page(s): 1850 - 1858
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (174 KB)  

    Low frequency reactive, resonant and negative resistance effects have been observed in backgate current flow in monolithic GaAs integrated circuits. Comparisons have been made between structures prepared by MBE on undoped buffer layers at high and low temperatures and by ion implantation. The study employed GaAs MESFETs which were similarly prepared on the three substrates. Backgate admittance spectroscopy measurements were performed between adjacent isolated n-type mesa structures on the different isolation materials in the range 10 Hz to 10 kHz, at temperatures ranging from 80 K to 340 K. In the case of the ion implanted and normally buffered structures the form of the susceptance frequency spectra depended on cathode size, dc bias and temperature and could include capacitive relaxation as well as inductive and capacitive behaviors separated by a resonance. The form of the variation of the conductance was closely associated and frequently included a frequency region within which there was negative small signal resistance. These effects were not present when the buffer layer was prepared at low temperatures. The results are summarized to make explicit the requirements of an explanatory model View full abstract»

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  • A comprehensive model of backgate impedance dispersions in GaAs isolation structures

    Publication Year: 2001 , Page(s): 1859 - 1869
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (209 KB)  

    A comprehensive model explains low frequency reactive, resonant and negative resistance effects in backgate current flow in monolithic GaAs integrated circuits. In a sister paper experimental comparisons were made between structures prepared by MBE on undoped buffer layers at high and low temperatures and by ion implantation. The study employed GaAs MESFETs which were similarly prepared on the three substrates. These observations provide the basis for the model. In the case of the ion implanted and normally buffered structures the form of the susceptance frequency spectra depended on cathode size, dc bias and temperature and could include capacitive relaxation as well as inductive and capacitive behaviors separated by a resonance. The form of the variation of the conductance was closely associated and frequently included a frequency region within which there was negative small signal resistance. All of these effects have been explained in terms of electron trapping at trap planes located at the interface between the n-type active region and the isolation material. In the case of inductive and capacitive relaxations a single trapping process was sufficient but the negative resistance behavior makes the additional requirement that charge should be trapped sequentially at least twice. Mathematical modeling and computational simulations have been used to give support to the physical models. In the case of the ion implanted structures it was possible to demonstrate reasonable quantitative agreement between the model and experiment using trap DLTS data View full abstract»

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  • OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current

    Publication Year: 2001 , Page(s): 2050 - 2057
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    In this work, an analytical model of the OFF-state leakage current in metal-oxide-semiconductor (MOS) transistors and its relation with the standby current of logic complementary MOS (CMOS) ICs is presented. The OFF leakage currents in (1) bulk MOS; (2) floating-body silicon-on-insulator (FB-SOI); and (3) body-tied SOI (BT-SOI) MOS field effect transistors (MOSFETs) are modeled based on physics mechanisms, equivalent circuits and operational block diagrams. Good correlation is obtained between the theory and experimental devices. The model clarifies and quantifies that in thin film FB-SOI, the OFF leakage current is dominated by (a) Vth at drain voltages lower than the onset of the “kink” effect Vds<Vdk , and (b) the impact ionization-induced floating-body effect for V ds>Vdk. The OFF-state leakage current model is successfully applied to the analysis and prediction of the leakage current components in logic integrated circuits (CMOS ICs) View full abstract»

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  • A CMOS integrated three-axis accelerometer fabricated with commercial submicrometer CMOS technology and bulk-micromachining

    Publication Year: 2001 , Page(s): 1961 - 1968
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (221 KB)  

    In this paper, a bulk-micromachined three-axis accelerometer fabricated with commercial submicrometer CMOS wafers has been developed for low-cost realization of smart accelerometers and improvement of device performance. The signal processing circuits for three-axis detection were formed using a commercial 0.8-μm CMOS technology. After that, micromachining processes were performed to the complete CMOS wafers to form accelerometer structures. The important technologies to separate micromachining processes from the CMOS process are wafer thickness control after CMOS fabrication and backside polishing with chemical spin etching. Accelerometers with 3×3 mm2 and 6×6 mm2 die size were fabricated with the developed fabrication technology. As a result of device evaluation, 2.0 mgrms resolution of Z-axis acceleration, and 10.8 mgrms resolution of X and Y-axis acceleration were obtained by the accelerometers with 6×6 mm2 die size. Comparing for the same die area, the 6×6 mm2 size accelerometer showed about 21.3 times higher resolution of Z-axis acceleration and 37.8 times higher resolution of X, Y-axis acceleration as compared to our previous three-axis accelerometer fabricated with 5.0-μm CMOS technology. Temperature dependence and reliability for repetitive vibration loads were also evaluated. Through these evaluations, basic performance of the CMOS integrated three-axis accelerometer has been confirmed View full abstract»

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  • Feasibility of 0.18 μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

    Publication Year: 2001 , Page(s): 2065 - 2073
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB)  

    A 0.18 μm silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications is demonstrated. The hybrid trench isolation is a combination of partial trench isolation and full trench isolation. In the partial trench isolation region, a part of the SOI layer remains under the field oxide so as to provide scalable body-tied SOI metal-oxide-semiconductor field-effect transistors (MOSFETs), while in the full trench isolation region, the whole of the SOI layer is replaced by the field oxide so as to provide high quality passives. It is demonstrated that this technology improves the maximum oscillation frequency and the minimum noise figure of the MOSFET and the Q-factor of the inductor, compared with bulk technology. Moreover, it is verified that the partial-trench-isolated body-tied structure suppresses the floating body effect of SOI devices for RF/analog applications and thus guarantees low-noise characteristics, stability, linearity, and reliability. It is concluded that this technology will be one of the key technologies for supporting the evolution of wireless communications View full abstract»

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  • Synthesis of a new manufacturable high-quality graded gate oxide for sub-0.2 μm technologies

    Publication Year: 2001 , Page(s): 2016 - 2021
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (149 KB) |  | HTML iconHTML  

    Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (TVE ) onto a pregrown low temperature thermally grown SiO2 layer to form a composite graded SiO2 structure. The cooling rate is carefully modulated near TVE~925°C to enhance growth induced stress relaxation. The pregrown SiO2 layer provides grading and is a sink for stress accommodation for the final high temperature SiO2 forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO2 interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, Cpk>1.5. Graded gate oxide is already in the primary path of our 0.16 μm and 0.12 μm technologies View full abstract»

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  • Development of robust interconnect model based on design of experiments and multiobjective optimization

    Publication Year: 2001 , Page(s): 1885 - 1891
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 μm CMOS technology; optimization results are discussed and verified using Monte Carlo simulation View full abstract»

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  • Calculation of the current response of the spatially modulated light CMOS detector

    Publication Year: 2001 , Page(s): 1892 - 1902
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB)  

    We present an analytical model that allows to calculate the current response of a spatially modulated light CMOS detector (SML-detector) and compare this response with the response of a traditional CMOS photodetector. It is shown that the SML detector already yields a three orders of magnitude faster response time than a traditional CMOS detector in a 0.25 μm CMOS technology. This response time will further decrease as CMOS technology evolves. This analytical expression is compared with a numerical solution of the diffusion equation and with experimental results. Both show an excellent correspondence. Therefore we can conclude that the SML-detector is the solution of choice for cheap, CMOS-compatible receivers in integrated opto-electronic systems View full abstract»

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  • An insulator-lined silicon substrate-via technology with high aspect ratio

    Publication Year: 2001 , Page(s): 2181 - 2183
    Cited by:  Papers (59)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (65 KB) |  | HTML iconHTML  

    We have developed a novel high-aspect ratio substrate-via technology in silicon that features a SiN insulator liner. In this technology, the via is completely filled with electroplated Cu. We have demonstrated vias with an aspect ratio of 30 and we have verified the integrity of the liner in vias with an aspect ratio of 8. The impedance of individual vias was measured in the microwave regime using a high-frequency test structure. The measured inductance of vias with aspect ratios between 3 and 30 approach the theoretically expected values View full abstract»

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  • Evaluation of high dose, high energy boron implantation into Cz substrates for epi-replacement in CMOS technology

    Publication Year: 2001 , Page(s): 2043 - 2049
    Cited by:  Papers (5)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    We implanted high energy boron to create a heavily doped ground plane in Cz wafers in order to replace p/p+ episubstrates in deep submicron complementary metal-oxide semiconductor (CMOS) technology. Devices manufactured on Cz wafers with a 1.5 or 1.6 MeV, 1×1015 cm-2 boron implanted ground plane have superior latch-up immunity as compared to devices on epiwafers. Improvements in latch-up suppression were observed for all isolation spacings. Diode leakage was lower in high dose buried-layer substrates than in episubstrates, while gate oxide integrity was equivalent. For the first time, buried layer substrates have been shown to duplicate or exceed the performance of episilicon simultaneously for all relevant CMOS transistor and circuit parameters View full abstract»

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  • Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors

    Publication Year: 2001 , Page(s): 2179 - 2181
    Cited by:  Papers (20)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (102 KB)  

    We discuss a previously overlooked gate resistance (Rg) component in silicided polysilicon-gate metal-oxide-semiconductor field-effect-transistors (MOSFETs). Since the high-frequency properties depend critically on Rg, this has motivated the recent addition of a resistive gate input in the BSIM3v3 MOSFET model. Our TLM results show that the contact resistance between silicide and polysilicon, built into the gate of a typical MOSFET, is of the same magnitude as the silicide sheet resistance. This contact resistance affects model scaling and will dominate Rg in narrow-width and short-channel MOS transistors View full abstract»

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  • Analysis of buried gate MESFET under dark and illumination

    Publication Year: 2001 , Page(s): 2138 - 2142
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB)  

    D.C. analysis has been carried out for a buried-gate GaAs metal semiconductor field effect transistor (MESFET) under dark and front illumination. The photovoltage I-V characteristics and the transconductance of the device have been evaluated. The results indicate very good performance of the device compared to other devices like MESFET under back illumination and MESFET with front illumination having surface gate. Thus, buried-gate optical field effect transistor (OPFET) will be highly suitable for optical communication and optical computing View full abstract»

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  • A comprehensive study of inversion current in MOS tunneling diodes

    Publication Year: 2001 , Page(s): 2125 - 2130
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB) |  | HTML iconHTML  

    The gate current of MOS tunneling diodes biased at inversion region with different substrate doping is investigated. For p-type substrate (1-5 Ω-cm) devices, the tunneling diode works in the deep depletion region and the inversion current is dominated by the thermal generation rate of minority electrons via traps at Si/SiO2 interface and in the deep depletion region. The activation energy is approximately equal to half of the silicon bandgap independent of gate voltage. For devices on p+ substrate (0.01-0.05 Ω-cm), the band-to-traps tunneling and band-to-band tunneling are the dominating current components at inversion bias, and reveal a strong field dependence and a weak temperature dependence. The band-to-traps and band-to-band current components are even more significant in the devices on the p++ substrate (0.001-0.0025 Ω-cm). Finally, the effects of temperature and light illumination on inversion current of MOS tunneling diodes will be also discussed View full abstract»

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  • A 30 frames/s 2/3-in 1.3 M-pixel progressive scan IT-CCD image sensor

    Publication Year: 2001 , Page(s): 1922 - 1928
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB)  

    A 30 frames/s 2/3-in 1.3 M-pixel progressive scan interline-transfer charge-coupled device (IT-CCD) image sensor has been developed for video and digital still-camera applications. To obtain high frame-rate images, a 49-MHz driving horizontal CCD (H-CCD) was developed. An 8-phase drive for vertical CCDs (V-CCDs) makes it possible to operate in a variety of modes, such as 1050 line progressive scan mode and 1049 line wide dynamic range interlaced scan mode. For digital still camera use, removing residual charges stored in the V-CCDs before exposure is essential, therefore new narrow-channel barrier over-flow drain (NCB-OFD) attached under the H-CCD was developed. The NCB-OFD automatically drains out extra charges and has the advantages of requiring neither an over-flow control gate nor any additional masks View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego