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IEEE Micro

Issue 3 • Date June 1990

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Displaying Results 1 - 5 of 5
  • Multiplexed buses: the endian wars continue

    Publication Year: 1990, Page(s):9 - 21
    Cited by:  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1026 KB)

    The issue of data exchange between type-1 and type-2 buses, which multiplex the first data byte (which has the lowest address) with the least and most significant portions of the address, respectively, is considered. In an analogy based on Gulliver's Travels, the associated architectures have been dubbed little-endian and big-endian processors, respectively. It is pointed out that the byte order w... View full abstract»

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  • The 68040 processor. 2. Memory design and chip

    Publication Year: 1990, Page(s):22 - 35
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1289 KB)

    For pt.1 see ibid., February (1990). The memory subsystem, the external bus, chip and board testing, and design-verification methods for the 68040, a third-generation, full-32-bit microprocessor in the Motorola 68000 family, are discussed. The internal caches and memory management are examined at length. The external bus protocol, arbitration, snooping, and timing specifications are addressed. The... View full abstract»

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  • The TMS390C602A floating-point coprocessor for Sparc systems

    Publication Year: 1990, Page(s):36 - 47
    Cited by:  Papers (2)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1221 KB)

    A recent Sparc (scalable processor architecture) processor consists of a two-chip configuration, containing the TMS390C601 integer unit (IU) and the TMS390C602A floating-point unit (FPU). The second device, an innovative coprocessor that lets the processor execute single- or double-precision floating-point instructions concurrently with IU operations is described. Dedicated floating-point hardware... View full abstract»

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  • Motorola's 88000 family architecture

    Publication Year: 1990, Page(s):48 - 66
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1670 KB)

    The initial members of the 88000 family of high-performance 32-bit microprocessor are the 88100 processor and the 88200 cache and memory management unit (CMMU). The processor manipulates integer and floating-point data and initiates instruction and data memory transactions. The CMMU minimizes the latency of main memory requests by maintaining a cache for data transaction and a cache for memory man... View full abstract»

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  • The Gmicro/300 32-bit microprocessor

    Publication Year: 1990, Page(s):68 - 75
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB)

    A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300's pipeline structur... View full abstract»

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Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center