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Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug. 2001

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Displaying Results 1 - 16 of 16
  • Editorial

    Publication Year: 2001 , Page(s): 1166
    Save to Project icon | Request Permissions | PDF file iconPDF (5 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • Editorial

    Publication Year: 2001 , Page(s): 1167
    Save to Project icon | Request Permissions | PDF file iconPDF (10 KB) |  | HTML iconHTML  
    Freely Available from IEEE
  • 100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications

    Publication Year: 2001 , Page(s): 1178 - 1185
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    A single-chip 100-Mbit/s burst-operation two-tap maximum likelihood sequence estimation (MLSE) equalizer LSI for QPSK signals is introduced. It also supports two-branch diversity combining. Three new techniques are used to realize this fast equalizer LSI: the quantized variable-gain least mean squares (VLMS) algorithm, which has small processing delay with fast convergence characteristics; a simple complex-valued multiplication scheme based on inverting the sign and switching the in-phase and quadrature-phase components; and a parallel structure to minimize the processing delay of path memory. The chip, containing 75 kgates, is manufactured using the 0.45-μm-CMOS gate array process. The supply voltage is 3.3 V. This LSI offers higher processing speed than any other conventional equalizer chip for mobile radio communications View full abstract»

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  • A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique

    Publication Year: 2001 , Page(s): 1281 - 1285
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate View full abstract»

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  • Design of low-voltage CMOS continuous-time filter with on-chip automatic tuning

    Publication Year: 2001 , Page(s): 1168 - 1177
    Cited by:  Papers (17)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V View full abstract»

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  • A GMSK modulator using a ΔΣ frequency discriminator-based synthesizer

    Publication Year: 2001 , Page(s): 1218 - 1227
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    This paper describes a new transmitter architecture suitable for wideband GMSK modulation. The technique uses direct modulation of ΔΣ frequency discriminator (ΔΣFD)-based synthesizer to produce the modulated RF signal without any up-conversion. Digital equalization is used to extend the modulation data rate far beyond the synthesizer closed-loop BW. A prototype 1.9-GHz GSM transmitter was constructed consisting of a ΔΣFD-based synthesizer and a digital transmit filter. The synthesizer consists of an 0.8-μm BiCMOS ΔΣFD chip, a digital signal processor FPGA, and an off-chip D/A converter, filter, and VCO. Measured results, using 271-kbit/s GSM modulation, demonstrate data rates well in excess of the 30-kHz synthesizer closed-loop BW are possible with digital equalization. Without modulation, the synthesizer exhibits a -76-dBc spurious noise level and a close-in phase noise of -74 dBc/Hz View full abstract»

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  • Conditional-capture flip-flop for statistical power reduction

    Publication Year: 2001 , Page(s): 1263 - 1271
    Cited by:  Papers (42)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-μm CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop View full abstract»

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  • A dual-band RF front-end for WCDMA and GSM applications

    Publication Year: 2001 , Page(s): 1198 - 1204
    Cited by:  Papers (80)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively View full abstract»

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  • A wide dynamic range receiver channel for a pulsed time-of-flight laser radar

    Publication Year: 2001 , Page(s): 1228 - 1238
    Cited by:  Papers (34)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    An integrated receiver channel for a pulsed time-of-flight (TOF) laser rangefinder has been designed and tested. The bandwidth of the receiver channel is 170 MHz, the transimpedance can be controlled in the range from 1.1 kΩ to 260 kΩ, and the input-referred noise is ~6 pA/√Hz. The distance measurement accuracy is ±4.7 mm (average of 10000 measurements), taking into account walk error (input signal amplitude varies in the range 1:624) and jitter. A considerable increase in the input dynamic range of the receiver has been achieved by placing an integrated current buffer with variable attenuation between the external photodetector and the transimpedance preamplifier. Integrated electronic gain control structures together with the small size and low power consumption achieved by the use of full custom integrated technology considerably simplifies rangefinding devices for many applications. The circuit was implemented in an 0.8-μm BiCMOS process View full abstract»

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  • Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic

    Publication Year: 2001 , Page(s): 1276 - 1280
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB) |  | HTML iconHTML  

    In this paper, a new charge-recycling differential logic named split-level precharge differential logic (SPDL) is presented. It employs a new push-pull type output driver which is simple and separated from the NMOS logic tree. Therefore, it can improve energy efficiency, driving capability, and reliability compared with the previous differential logic structures which use cross-coupled inverters as the output driver. To verify the reliability and the applicability of the proposed SPDL in VLSI systems, an 8-bit full adder is fabricated in a 0.6-μm CMOS technology. Experimental results show that the performance of the SPDL is about two times as good as that of the previous half-rail differential logic (HRDL) in terms of power-delay product. Moreover, the SPDL has stable operation under mismatch or parameter variation View full abstract»

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  • A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

    Publication Year: 2001 , Page(s): 1186 - 1197
    Cited by:  Papers (42)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB) |  | HTML iconHTML  

    This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA View full abstract»

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  • Analysis and design of high-speed and low-power CMOS PLAs

    Publication Year: 2001 , Page(s): 1250 - 1262
    Cited by:  Papers (22)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB) |  | HTML iconHTML  

    The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are analyzed first to find out their speed and power bottlenecks. Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time. Finally, high speed is achieved through the combined effect of utilization of a fast pseudofootless dynamic circuit and a reduced interplane clock delay. On the other hand, low power is achieved because the power consumption from the three main sources, i.e., the AND-plane circuits, the interplane buffers, and the OR-plane circuits, can be reduced significantly and simultaneously. The delay time and the power consumption of the critical path of a PLA are taken as the performance evaluation parameters. When the 50×50×64 PLAs are designed in a 0.35-μm 1P4M CMOS technology, the maximum operating frequency of the proposed PLA is 1.61 times higher than that of the fastest conventional PLA. Furthermore, power reduction can be as high as 18% and 43% when the operating frequencies are set to be 100 MHz and 50 MHz, respectively, as compared to the most power-efficient conventional PLA View full abstract»

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  • Adaptive analog IF signal processor for a wide-band CMOS wireless receiver

    Publication Year: 2001 , Page(s): 1205 - 1217
    Cited by:  Papers (21)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    An IF strip for a wireless receiver supports a variable baud rate by changing analog filter bandwidth. Sliding and step adaptive dynamic range are both used at IF to dissipate only the necessary power at prevailing channel conditions. A combination of VGA and PGA is developed for 64-QAM. The total signal processor draws an average of 16 mA from 3.3 V and a peak of 73 mA. The differential input noise is as low as 3.9 nV/√Hz, while maximum IIP3 is +22 dBm with respect to 100 ohms View full abstract»

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  • A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution

    Publication Year: 2001 , Page(s): 1286 - 1290
    Cited by:  Papers (10)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB) |  | HTML iconHTML  

    This paper describes a programming circuit for analog memory using pulsewidth modulation (PWM) signals and the circuit performance obtained from measurements using a floating-gate EEPROM device. This programming circuit attains both high programming speed and high precision. We fabricated the programming circuit using standard 0.6-μm CMOS technology and constructed an analog memory using the programming circuit and a floating-gate MOSFET. The measurement results indicate that the analog memory attains a programming time of 75 μs, an updating resolution of 11 bit, and a memory setting precision of 6.5 bit. This programming circuit can be used for intelligent information processing hardware such as self-learning VLSI neural networks as well as multilevel flash memory View full abstract»

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  • Asynchronous cross-pipelined multiplier

    Publication Year: 2001 , Page(s): 1272 - 1275
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    In this paper, a design of a 16-bit asynchronous multiplier is presented. The multiplier core consists of small basic blocks. Each block includes handshake and computation logic and communicates with four neighbor cells in asynchronous handshake fashion using four-phase protocol. The computation logic is implemented in dual-rail coded domino logic. The input and output signals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four-phase signaling. The design speed is self-adjusting to the technology parameters and supply voltage variations. The multiplier has low latency and achieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6-μm CMOS process and has a core size of 4.3×2.1 mm View full abstract»

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  • Low switching noise and load-adaptive output buffer design techniques

    Publication Year: 2001 , Page(s): 1239 - 1249
    Cited by:  Papers (20)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per VDD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan