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Electron Device Letters, IEEE

Issue 8 • Date Aug. 2001

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Displaying Results 1 - 17 of 17
  • 300 GHz InP/GaAsSb/InP double HBTs with high current capability and BV/sub CEO/>6 V

    Publication Year: 2001 , Page(s): 361 - 363
    Cited by:  Papers (81)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB)  

    We report MOCVD-grown NpN InP/GaAsSb/InP abrupt double heterojunction bipolar transistors (DHBTs) with simultaneous values of f/sub T/ and f/sub MAX/ as high as 300 GHz for J/sub C/=410 kA/cm/sup 2/ at V/sub CE/=1.8 V. The devices maintain outstanding dynamic performances over a wide range of biases including the saturation mode. In this material system the p+ GaAsSb base conduction band edge lies 0.10-0.15 eV above the InP collector conduction band, thus favoring the use of nongraded base-collector designs without the current blocking effect found in conventional InP/GaInAs-based DHBTs. The 2000 /spl Aring/ InP collector provides good breakdown voltages of BV/sub CEO/=6 V and a small collector signal delay of /spl sim/0.23 ps. Thinner 1500 /spl Aring/ collectors allow operation at still higher currents with f/sub T/>200 GHz at J/sub C/=650 kA/cm/sup 2/. View full abstract»

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  • High performance 0.35 μm gate-length monolithic enhancement/depletion-mode metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As HEMTs on GaAs substrates

    Publication Year: 2001 , Page(s): 364 - 366
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB)  

    Monolithic integration of enhancement (E)- and depletion (D)-mode metamorphic In/sub 0.52/Al/sub 0.48/As/In/sub 0.53/Ga/sub 0.47/As/GaAs HEMTs with 0.35 μm gate-length is presented for the first time. Epilayers are grown on 3-inch SI GaAs substrates using molecular beam epitaxy. A mobility of 9550 cm2/V-s and a sheet density of 1.12×10/sup 12/ /sup -2/ are achieved at room temperature. Buried Pt-gate was employed for E-mode devices to achieve a positive shift in the threshold voltage. Excellent characteristics are achieved with threshold voltage, maximum drain current, and extrinsic transconductance of 100 mV, 370 mA/mm and 660 mS/mm, respectively for E-mode devices, and -550 mV, 390 mA/mm and 510 mS/mm, respectively for D-mode devices. The unity current gain cutoff frequencies of 75 GHz for E-mode and 80 GHz for D-mode are reported. View full abstract»

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  • Ultra-short 25-nm-gate lattice-matched InAlAs/InGaAs HEMTs within the range of 400 GHz cutoff frequency

    Publication Year: 2001 , Page(s): 367 - 369
    Cited by:  Papers (29)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (97 KB) |  | HTML iconHTML  

    We have succeeded in fabricating ultra-short 25-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates. The two-step-recessed gate technology and low temperature processing at below 300/spl deg/C allowed the fabrication of such ultra-short gates. DC measurements showed that the 25-nm-gate HEMT had good pinchoff behavior. We obtained a cutoff frequency f/sub T/ of 396 GHz, within the range of 400 GHz f/sub T/, for the 25-nm-gate HEMT. This f/sub T/ is the highest value get reported for any type of transistor, and the gate length of 25 nm is the shortest value ever reported for any compound semiconductor transistor that exhibits device operation. View full abstract»

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  • Unilateral power gain limitations due to dynamic base widening effects

    Publication Year: 2001 , Page(s): 370 - 372
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (59 KB) |  | HTML iconHTML  

    It is shown that the maximum frequency of oscillation of an InP-HBT may be limited by the low velocity of the holes when operated in the base push-out regime since modulation of the extended base will be delayed by the hole transit time, having an effect also on the electron current. The resulting delay of the current response causes a peaking of the unilateral power gain followed by a -40 dB/decade roll-off, being a source for a strong overestimation of the extrapolated cut-off frequency when neglected. An extended equivalent small-signal circuit is proposed that takes these effects into account. View full abstract»

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  • RESURF AlGaN/GaN HEMT for high voltage power switching

    Publication Year: 2001 , Page(s): 373 - 375
    Cited by:  Papers (19)  |  Patents (42)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (77 KB) |  | HTML iconHTML  

    A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage >1 KV at on-resistance of /spl sim/1 m/spl Omega//spl middot/cm/sup 2/ (neglecting contact resistances) for the device. View full abstract»

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  • High-frequency measurements of AlGaN/GaN HEMTs at high temperatures

    Publication Year: 2001 , Page(s): 376 - 377
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB) |  | HTML iconHTML  

    High-frequency measurements of the 1.3-μm-long gate AlGaN-GaN HEMTs have been performed at temperatures ranging from 23 to 187/spl deg/C. The cutoff frequency fT decreased with increasing temperature. It was 13.7 and 8.7 GHz at 23 and 187/spl deg/C, respectively. The effective electron velocities /spl upsi//sub eff/ in the channel evaluated from the total delay time versus I/sub D/-inverse relation were 1.2 and 0.8×10/sup 7/ cm/s at 23 and 187/spl deg/C, respectively. View full abstract»

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  • Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion

    Publication Year: 2001 , Page(s): 378 - 380
    Cited by:  Papers (11)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB) |  | HTML iconHTML  

    Ultrathin thermally enhanced remote plasma nitrided oxides (TE-RPNO) with equivalent oxide thickness down to 1.65 nm are fabricated to investigate their leakage current reduction and boron diffusion barrier performances. A PMOSFET with TE-RPNO, compared to its conventional oxide counter-part, yields almost one order magnitude lower gate leakage current, less flatband voltage changes in high boron implantation dose or activation temperature, and shows broader process windows in the tradeoff between boron penetration and dopant activation. View full abstract»

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  • Model of low frequency noise in polycrystalline silicon thin-film transistors

    Publication Year: 2001 , Page(s): 381 - 383
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB) |  | HTML iconHTML  

    A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements. View full abstract»

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  • High quality thermal oxide on LPSOI formed by high temperature enhanced MILC

    Publication Year: 2001 , Page(s): 384 - 386
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (111 KB) |  | HTML iconHTML  

    The characteristics of thermal polyoxide grown on large-grain polysilicon-on-insulator (LPSOI) formed by high temperature enhanced metal-induced-lateral-crystallization (MILC) have been investigated. Compared with conventional polysilicon films, LPSOI films have reduced surface roughness and a smaller number of grain boundaries. The improved polysilicon quality leads to better thermal oxide quality, especially at device dimensions that are smaller than the grain size. Intrinsic oxide characteristics such as breakdown voltage, leakage current and charge-to-breakdown value have been experimentally measured. Significant improvement in both oxide quality and device-to-device variation is reported. View full abstract»

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  • High quality gate dielectrics grown by rapid thermal processing using split-N2O technique on strained-Si/sub 0.91/Ge/sub 0.09/ films

    Publication Year: 2001 , Page(s): 387 - 389
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB) |  | HTML iconHTML  

    Thermal stability and strain relaxation temperature of strained Si/sub 0.91/Ge/sub 0.09/ layers has been investigated using double crystal x-ray diffraction (DCXRD). High quality gate oxynitride layers rapid thermally grown on strained Si/sub 0.91/Ge/sub 0.09/ using N/sub 2/O and the split N/sub 2/O cycle technique below the strained relaxed temperature is reported. A positive fixed oxide charge density was observed for N/sub 2/O and split-N/sub 2/O grown films. The O/sub 2/ grown films exhibit a negative fixed oxide charge. The excellent improvements in the leakage current, breakdown field and charge-to-breakdown value of the N/sub 2/O or split-N/sub 2/O grown films were achieved compared to pure O/sub 2/ grown films. View full abstract»

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  • High-frequency performance of diamond field-effect transistor

    Publication Year: 2001 , Page(s): 390 - 392
    Cited by:  Papers (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 μm and a source-gate spacing of 0.1 μm were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 μm gate MESFET at V/sub GS/=-1.5 V and V/sub DS/=-5 V,for which a cutoff frequency fT and a maximum oscillating frequency fmax of 2.2 GHz and 7 GHz were obtained, respectively. View full abstract»

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  • A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

    Publication Year: 2001 , Page(s): 393 - 395
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB)  

    A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (/spl les/600/spl deg/C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm/sup 2//V-s and 6/spl times/10/sup 6/ respectively. View full abstract»

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  • Poly-Si TFT fabricated by laser-induced in-situ fluorine passivation and laser doping

    Publication Year: 2001 , Page(s): 396 - 398
    Cited by:  Papers (10)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB)  

    A new poly-Si TFT has been fabricated by employing laser-induced in-situ fluorine passivation and a laser-doping method. With only one excimer laser annealing, we have successfully fabricated the device using one step to crystallize, passivate and dope simultaneously. Although no additional plasma post-passivation was performed, the on-state and the off-state leakage properties of TFTs with fluorine passivation were improved compared with those without fluorine passivation. The device with in-situ fluorine passivation has the maximum transconductance of 13.3 μA/V for a C2F/sub 6/ flow rate of 100 sccm, whilst that for a device without fluorine passivation is 8.4 μA/V. The device reliability under electrical stress was remarkably improved in the in-situ fluorine-passivated devices due to the fluorine passivation of trap states in the poly-Si channel and at the SiO2/poly-Si interface. View full abstract»

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  • Fabrication of microcrystalline silicon TFTs using a high-density plasma approach

    Publication Year: 2001 , Page(s): 399 - 401
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (55 KB) |  | HTML iconHTML  

    N-channel microcrystalline silicon (mc-Si) thin film transistors (TFTs) were fabricated using a high density plasma (HDP) approach. An electron cyclotron resonance (ECR) plasma source was employed to deposit all of the thin film materials needed for the transistor; that is, intrinsic mc-Si, n-type mc-Si, and dielectric silicon dioxide were grown with the ECR high density plasmas and the deposition rates for these films were in the range of 120-150 /spl Aring//min. The substrate temperatures during these depositions were maintained below 285/spl deg/C. To complete the fabrication of these TFTs, we used only two masks with one alignment. After 1 h annealing under forming gas atmosphere, the mc-Si TFTs perform with linear field effect mobility of 12 cm2/V-s, on/off ratio of 106, subthreshold swing of 0.3 V/decade, off-current of 4×10/sup -13/ A/μm and threshold voltage of 5 V. View full abstract»

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  • A poly-Si TFT integrated gate-data line-crossover structure employing an air-gap for large-size AMLCD panel

    Publication Year: 2001 , Page(s): 402 - 404
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (60 KB) |  | HTML iconHTML  

    We have fabricated a novel poly-Si TFT integrated at the gate-data line-crossover structure without sacrificing the electrical characteristics. The aperture ratio of the panel was increased considerably because the TFT was located under the opaque metal line. In particular, we employed a low dielectric air-gap between the gate line and data lines, which reduced capacitance between the gate and data lines, enabling the signal delay of the data line to be significantly decreased. The fabricated TFT was successfully operated, and the proposed structure found to reduce the delay time by a factor of nine compared with conventionally constructed panel without air-bridges. View full abstract»

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  • Pi-Gate SOI MOSFET

    Publication Year: 2001 , Page(s): 405 - 406
    Cited by:  Papers (90)  |  Patents (79)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (40 KB) |  | HTML iconHTML  

    This paper describes computer simulations of various SOI MOSFETs with double and triple gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "/spl Pi/-gate" or "Pi-gate" MOSFET) is introduced, The proposed device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. View full abstract»

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  • Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices

    Publication Year: 2001 , Page(s): 407 - 409
    Cited by:  Papers (26)  |  Patents (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB) |  | HTML iconHTML  

    The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance requirement and inter-diffusion problem. We report a novel device structure termed oxide-bypassed VDMOS (OBVDMOS) that requires the well-established oxide thickness control instead of the difficult doping control in translating the limit to a higher blocking voltage. This is done by using metal-thick-oxide (MTO) at the sidewalls of drift region. One can choose to have a higher blocking voltage or increase the background doping. A PiN structure, essentially identical to MOSFET during off state, was fabricated to demonstrate the proposed concept. Its measured BV/sub dss/ of 170 V is 2.5 times higher than measured conventional device BV/sub dss/ of 67 V on the same silicon wafer. View full abstract»

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