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IEE Proceedings - Computers and Digital Techniques

Issue 3 • Date May 2001

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Displaying Results 1 - 5 of 5
  • Multiple-path ATM switch architecture for dynamic VC establishment

    Publication Year: 2001, Page(s):119 - 127
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (932 KB)

    The paper presents a novel ATM switch architecture to support a multiple-path virtual channel (MPVC). Based on an internal cell loss threshold the switch can dynamically change its hardware structure from a single-path to a multiple-path VC. Two algorithms are developed to cope with the dynamic nature of switch architectures. The first, bandwidth allocation algorithm (BAA), is used to reserve band... View full abstract»

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  • Comment on Lin-Wu (t, n)-threshold verifiable multisecret sharing scheme

    Publication Year: 2001
    Cited by:  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (92 KB)

    T.Y. Lin and T.C. Wu (1999) gave a (t, n)-threshold verifiable multisecret sharing scheme ((t, n)-VMSS) of the following kind. A secret dealer (SD) issues secret shares to each of n participants, and any more than t participants can cooperatively reconstruct the secrets. The purpose of this paper is to paint out that the claim made previously by the authors, that their scheme is secure against che... View full abstract»

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  • High-bandwidth x86 instruction fetching based on instruction pointer table

    Publication Year: 2001, Page(s):113 - 118
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (676 KB)

    Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a cycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing a... View full abstract»

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  • Multiple-level logic simulation algorithm

    Publication Year: 2001, Page(s):129 - 137
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1040 KB)

    An algorithm for the simulation of gate-level logic is presented. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analogue simulator. A Boolean equation solver is incorporated to fin... View full abstract»

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  • Memory access optimisation for reconfigurable systems

    Publication Year: 2001, Page(s):105 - 112
    Cited by:  Papers (13)  |  Patents (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (884 KB)

    Memory access optimisation for FPGA-based reconfigurable systems with a hierarchy of on-chip and off-chip (external) memory to speed up applications limited by memory access speed are discussed. Most of the techniques are also valid for dedicated embedded systems and system-on-a-chip (SoC) designs. The approach involves two kinds of optimisation: first, methods to reduce the number of accesses by ... View full abstract»

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