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Computers and Digital Techniques, IEE Proceedings -

Issue 3 • Date May 2001

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Displaying Results 1 - 5 of 5
  • Multiple-path ATM switch architecture for dynamic VC establishment

    Page(s): 119 - 127
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    The paper presents a novel ATM switch architecture to support a multiple-path virtual channel (MPVC). Based on an internal cell loss threshold the switch can dynamically change its hardware structure from a single-path to a multiple-path VC. Two algorithms are developed to cope with the dynamic nature of switch architectures. The first, bandwidth allocation algorithm (BAA), is used to reserve bandwidth evenly for a call request that requires the support of a multiple-path VC. The second, cell resequencing algorithm (CRA), is applied to reorder the cell sequence at every extra switch stage, when a single-path VC is changed to a multiple-path VC. The paper analyses the MPVC architecture using both mathematical and simulation models. Then, it compares the performance of using a single-path VC and a multiple-path VC, respectively, in terms of end-to-end cell transfer delay, cell loss ratio, and effective VC throughput under different traffic loads and buffer sizes View full abstract»

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  • High-bandwidth x86 instruction fetching based on instruction pointer table

    Page(s): 113 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    Providing higher degree superscalar instruction fetching is a major concern in a high performance superscalar processor design. In x86 architectures, the variable-length instructions make fetching multiple instructions in a cycle difficult. A common practice is to use predecoded information to help in instruction fetching, while the complex instruction formats induce high redundancies in storing and processing the pre-decoded information in the cache. In the paper, the authors propose to use an instruction identifier to predict instruction length and store the instruction pointers as superscalar instruction group indicators. With this method, the difficulty of achieving a high instruction fetch degree (>3) can be overcame. Simulation results suggest that the Instruction Identifier with a 64-entry table is a good performance/cost choice. In the meantime, as the table size decreases, the prediction scheme becomes increasingly important. Moreover, simulation and circuit synthesis show that this design is feasible for high clock rate design View full abstract»

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  • Comment on Lin-Wu (t, n)-threshold verifiable multisecret sharing scheme

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (92 KB)  

    T.Y. Lin and T.C. Wu (1999) gave a (t, n)-threshold verifiable multisecret sharing scheme ((t, n)-VMSS) of the following kind. A secret dealer (SD) issues secret shares to each of n participants, and any more than t participants can cooperatively reconstruct the secrets. The purpose of this paper is to paint out that the claim made previously by the authors, that their scheme is secure against cheating by a participant, is false. Further, the cheater might also be the only one who obtains the secret View full abstract»

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  • Multiple-level logic simulation algorithm

    Page(s): 129 - 137
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1040 KB)  

    An algorithm for the simulation of gate-level logic is presented. Multiple logic levels are used to describe the state of each node. Each state corresponds to a different voltage level, and the number of levels to be used for a simulation is user-defined. This feature simplifies considerably the interface between a digital and an analogue simulator. A Boolean equation solver is incorporated to find the initial operating point of a circuit before a transient analysis begins. This solver has the capability of finding the operating point of gates located in feedback loops, and to determine whether the network has no, one or multiple solutions. In the latter case, the solver can identify the nodes whose values are undetermined, thus avoiding the need to initialize all nodes in the network to an unknown state `X'. For transient analysis, a gate delay model that takes into account the slope of the input waveforms is used. The performance of the algorithm is demonstrated by simulations of a number of benchmark circuits View full abstract»

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  • Memory access optimisation for reconfigurable systems

    Page(s): 105 - 112
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    Memory access optimisation for FPGA-based reconfigurable systems with a hierarchy of on-chip and off-chip (external) memory to speed up applications limited by memory access speed are discussed. Most of the techniques are also valid for dedicated embedded systems and system-on-a-chip (SoC) designs. The approach involves two kinds of optimisation: first, methods to reduce the number of accesses by caching repeatedly used values are considered. The notion of vector access equivalence is introduced to form the basis of techniques employing FPGA storage as shift registers for caching. Larger data sets can be stored, if possible, in FPGA on-chip RAMs; RAM inference, a technique to automatically extract small on-chip RAMs to reduce external memory accesses is presented. Secondly, the authors aim to minimise the time spent on accesses to bandwidth-limited external memory, by scheduling as many accesses in parallel as possible. They present a technique which optimally allocates program arrays to memory banks, thereby minimising the overall access time. It also determines the most effective addressing mode for memory which can be accessed using different bitwidths View full abstract»

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