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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 4 • Date Apr 2001

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Displaying Results 1 - 14 of 14
  • Nested Miller compensation in low-power CMOS design

    Page(s): 388 - 394
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    First, new stability conditions for low-power CMOS nested Miller compensated amplifiers are given in this brief. Then, an improved structure, which takes the advantages of a feedforward transconductance stage and a nulling resistor, is introduced. Experimental results prove that the proposed structure improves the frequency response, transient response, and power supply rejection ratio without increasing the power consumption and circuit complexity View full abstract»

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  • Versatile insensitive current-mode universal biquad implementation using current conveyors

    Page(s): 409 - 413
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB) |  | HTML iconHTML  

    We present a versatile multi-input-multi-output biquad configuration. Either a three-input single-output or a single-input three-output universal filter can be realized. The proposed construction is comprised of only three current conveyors and four grounded passive elements, is multifunctional and convenient for monolithic integration, has low sensitivity, and is simple in structure. Its high impedance outputs enable easy cascading in current-mode operation. After slightly modifying an original configuration, another novel single-input three-output universal filter with extra advantageous features has been obtained. The effects of current conveyor nonidealities are discussed and simulation results are provided View full abstract»

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  • A high-selectivity switched-capacitor bandpass filter

    Page(s): 351 - 358
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    A high-selectivity switched-capacitor bandpass filter is presented. The filter center frequency is 100 kHz with a -3 dB bandwidth of 980 Hz (i.e., with a quality factor Q~100). This has been implemented with a 12th-order transfer function whose poles are placed at only two frequencies. This choice has been used in the integrated circuit realization. In fact, the transfer function has been implemented using the cascade of six biquad cells of only two types. For the available 20 samples, the center frequency mean-value error is lower than 0.2%, and the Q mean-value error is lower than 0.2% as well. The filter is realized in a not-recent BiCMOS technology (LNMOS=4 μm, L PMOS=3 μm). The same performance (opamp, switches, and overall filter) can be easily obtained with a standard scaled-down (0.35 μm, for instance) CMOS technology. In this direction, an evaluation of the area and power consumption of the circuit as implemented in a standard 0.35-μm CMOS technology is finally given View full abstract»

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  • Fundamental frequency response bounds of direct-form recursive switched-capacitor filters with capacitance mismatch

    Page(s): 340 - 350
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB) |  | HTML iconHTML  

    A theoretical statistical analysis is developed to investigate the effects of random capacitance matching errors in the frequency response of recursive switched-capacitor filters implemented in direct form. As a result, with appropriate approximations, closed-form solutions for the mean and the standard deviation of the frequency response error are derived. The obtained expressions provide insight into the quantitative influence of capacitance ratio tolerance, numerator and denominator orders, passband and stopband ripples, and edge frequencies, and reveal existing tradeoffs among these parameters, so that the most efficient filter design can be found. The main theoretical results are extensively verified by simulation through Monte Carlo analysis to show the effectiveness of the proposed formulas View full abstract»

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  • A generalized direct-form delta operator-based IIR filter with minimum noise gain and sensitivity

    Page(s): 425 - 431
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    This brief presents the derivation of an arbitrary order delta operator-based direct-form IIR filter with minimum roundoff noise gain and sensitivity. It utilizes the concept of different coupling coefficients at different branch nodes for better noise gain suppression. Two possible structures for realizing the inverse delta operator are considered and procedures for calculating the optimal filter coefficients are given. By means of state-space representation and matrix manipulation, it is also shown that expressions for sensitivity measures of different filter coefficients and their corresponding roundoff noise gain expressions are the same. This enables the simultaneous minimization of sensitivity and noise power for the proposed generalized filter structure View full abstract»

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  • Multichannel regularized recovery of compressed video sequences

    Page(s): 376 - 387
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB) |  | HTML iconHTML  

    In this paper, we propose a multichannel regularized recovery approach to ameliorate coding artifacts in compressed video. The major advantage of the proposed approach is that both temporal and spatial correlations in a video sequence can be exploited to complement the compressed video data. In particular a temporal regularization term is introduced to enforce smoothness along the motion trajectories defined by the transmitted motion vectors for motion compensation. Several forms of temporal regularization with different computational complexity are considered. Based on the proposed approach, recovered images are obtained from the compressed data using the well-known gradient-projection algorithm. Moreover, an iterative algorithm is proposed for the determination of regularization parameters at the coder side. A number of numerical experiments using several H.261 and H.263 compressed streams are presented to evaluate the performance of the proposed recovery algorithms. Results from these experiments demonstrate that the use of temporal regularization ran yield significant improvement in the quality of the recovered images-in terms of both visual evaluation and objective peak-signal-to-noise (PSNR) measure View full abstract»

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  • Design and analysis of a portable high-speed clock generator

    Page(s): 367 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    A new portable clock generator with full pull-in range and fast acquisition is presented in this paper, where it can be developed at hardware description language (HDL) to reduce design cycle as well as improve system-level integration simulation. In the proposed design, frequency tracking is performed by the “Prune-and-Search” algorithm, and the digital-controlled ring oscillator is constructed by CMOS standard cells. In order to reduce propagation delay of the loop divider, a novel structure is developed to provide a constant delay at any divider setting. In addition, input jitter can be isolated to avoid coupling by digital processing. Hence, the generated clock output becomes more clean and robust. Based on the proposed methodology, a test chip has been designed and verified on 0.6-μm CMOS process with frequency range of (360 ~ 800) MHz at 3.3 V and peak-to-peak jitter of less than 60 ps at 800 MHz/3.3 V View full abstract»

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  • Syllabic-companding log domain filters

    Page(s): 329 - 339
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    A general theory for companding log domain filters is proposed which combines not only exponential mappings, but also a new translational mapping approach which guarantees suitable operating conditions in any log domain filter. The filter equations resulting from the use of the theory ultimately contain translinear terms which are known to be realizable using translinear techniques. A discussion of the design of the companding filters, regarding the economical use of translinear loops and the convenient selection of system parameters, is offered which leads to first- and second-order circuit designs. Finally, the noise performance of an example design is investigated using a carefully crafted large-signal simulation technique, showing clearly the advantage of the companding filter approach View full abstract»

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  • High-valued passive element simulation using low-voltage low-power current conveyors for fully integrated applications

    Page(s): 405 - 409
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB) |  | HTML iconHTML  

    In this brief, we describe how, using low-voltage low-power second-generation current conveyors, it is possible to simulate the frequency behavior of high capacitances and inductances by utilizing only elements suitable for an integrated implementation. The effect of current conveyor nonidealities has been taken into account. The simulated inductances and capacitances have been utilized, as an example, in the design of a fully integrated bandpass filter. PSPICE simulations, performed employing a standard CMOS technology (ALCATEL Mietec 0.5 μm) and showing good performance of the presented circuits, are also reported View full abstract»

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  • Some space considerations of VLSI systolic array mappings

    Page(s): 419 - 424
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB) |  | HTML iconHTML  

    In this brief, the space-time mapping of the dependency matrix of an algorithm is used to study spatial properties of a systolic array implementation of a three-nested loop structure. Elementary expressions are developed for both the number of processing elements and the area of the array. These expressions involve only the space-time transformation and the lengths of the loops. As well, characterizations have been found for the form of the space-time transformation which produces a systolic array with the minimum number of processing elements, and one which has both the minimum number of processing elements and the smallest area. Moreover, the approaches can also be extended to general algorithms, such as variable loop lengths View full abstract»

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  • An efficient systolic architecture for the DLMS adaptive filter and its applications

    Page(s): 359 - 366
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    In this paper, we propose an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying our tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal View full abstract»

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  • A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 ms/s

    Page(s): 394 - 399
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    The problem of realizing low-voltage SC circuits is addressed. The case of using standard CMOS technology without on-chip multiplication is focused on. In this situation, a tradeoff between a high sampling frequency and a large output swing is present. In fact the switched-op-amp technique guarantees rail-to-rail output swing but at a low (<4 MHz) sampling frequency. The use of standard structures at a reduced output swing allows one to operate at a much higher sampling frequency (≈40 MHz). This concept is demonstrated here with experimental results from a 1.2-V 600-μW SC double-sampled pseudodifferential sample-and-hold (S&H) circuit realized in a standard 0.5-μm CMOS technology without using an on-chip voltage multiplier. With a 600-mVpp signal at 2 MHz using a 40-MHz sampling frequency, the sample-and-hold exhibits a total harmonic distortion better than -50 dB and a CMR better than -40 dB View full abstract»

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  • Analog implementation of an active noise controller system for portable audio applications

    Page(s): 400 - 404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    The active noise controller (ANC) system described here implements a practical design that significantly decreases background noise of signals common to most portable audio devices. This is achieved by a mixture of conventional ANC blocks with less traditional implementations, including a combined FIR/IIR structure using switched-capacitor blocks such as summers, integrators, multipliers, and delays. The proposed design also works as a stand-alone system and it has been successfully implemented on a 1.2-μm CMOS technology View full abstract»

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  • Modeling CMOS gates driving RC interconnect loads

    Page(s): 413 - 418
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB) |  | HTML iconHTML  

    The problem of estimating the performance of CMOS gates driving RC interconnect loads is addressed in this paper. The widely accepted π-model is used for the representation of an interconnect line that is driven by an inverter. The output waveform and the propagation delay of the inverter are analytically calculated taking into account the coupling capacitance between input and output and the effect of the short-circuit current. In addition, short-circuit power dissipation is accurately estimated. Once the voltage waveform at both the beginning and the end of an interconnect line are obtained, a simple method is employed in order to calculate the voltage waveform at each point of the line View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope