Issue 4 • Date Aug. 2001
Filter Results
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Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs
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PDF (156 KB)
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An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
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PDF (266 KB)
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Correction to "Design of synchronous and asynchronous variable-latency pipelined multipliers"
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PDF (60 KB)
Aims & Scope
IEEE Transactions on Very Large Scale Integration (VLSI) Systems includes all major aspects of the design and implementation of VLSI/ULSI and microelectronic systems.
Meet Our Editors
Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
tvlsieic@eecs.northwestern.edu


